MAX1266BEEI+ Maxim Integrated Products, MAX1266BEEI+ Datasheet - Page 13

• Manufacturer Part Number: MAX1266BEEI+
• Description: IC ADC 12-BIT 420KSPS 28-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1266BEEI+

• Number Of Bits: 12
• Sampling Rate (per Second): 420k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Number Of Adc Inputs: 6
• Architecture: SAR
• Conversion Rate: 420 KSPs
• Resolution: 12 bit
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To select external clock mode, bits D6 and D7 of the
control byte must be set to 1. Figure 6 shows the clock
and WR timing relationship for internal (Figure 6a) and
external (Figure 6b) acquisition modes with an external
clock. For proper operation, a 100kHz to 7.6MHz clock
frequency with 30% to 70% duty cycle is recommended.
Operating the MAX1266/MAX1268 with clock frequen-
cies lower than 100kHz is not recommended, because
the resulting voltage droop across the hold capacitor in
the T/H stage degrades performance.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
CLK
CLK
WR
WR
CLK
CLK
WR
WR
with +2.5V Reference and Parallel Interface
ACQMOD = 1
ACQMOD = 1
t
CWH
______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
ACQMOD = 0
ACQUISITION STARTS
ACQMOD = 0
ACQUISITION STARTS
t
t
DH
DH
ACQUISITION STARTS
External Clock Mode
ACQUISITION STARTS
t
CWS
t
CH
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
t
CP
t
CL
WR GOES HIGH WHEN CLK IS LOW
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
ACQUISITION ENDS
The input and output data are multiplexed on a tri-state
parallel interface (I/O) that can easily be interfaced with
standard µPs. The signals CS, WR, and RD control the
write and read operations. CS represents the chip-
select signal, which enables a µP to address the
MAX1266/MAX1268 as an I/O port. When high, CS dis-
ables the CLK, WR, and RD inputs and forces the inter-
face into a high-impedance (high-Z) state.
ACQUISITION ENDS
t
CWH
ACQUISITION ENDS
ACQMOD = 0
CONVERSION STARTS
CONVERSION STARTS
ACQMOD = 0
t
CWS
CONVERSION STARTS
CONVERSION STARTS
Digital Interface
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