MAX1145BEAP+ Maxim Integrated Products, MAX1145BEAP+ Datasheet - Page 7

• Manufacturer Part Number: MAX1145BEAP+
• Description: IC ADC 14BIT 150KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1145BEAP+

• Number Of Bits: 14
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Conversion Rate: 150 KSPs
• Resolution: 14 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Snr: 82 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
SSTRB
NAME
AGND
DGND
DGND
AGND
SHDN
DOUT
DV
AV
AV
SCLK
CREF
REF
RST
DIN
AIN
CS
P2
P1
P0
DD
DD
DD
14-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________
ADC Reference Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with 4.7µF capacitor.
Analog Supply. Connect to pin 4.
Analog Ground. This is the primary analog ground (star ground).
Analog Supply, 3.3V ±5%. Bypass AV
Digital Ground
Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
User-Programmable Output 2
User-Programmable Output 1
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before
the MSB decision. It is high impedance when CS is high in external clock mode.
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode SCLK sets the conversion speed.
Digital Ground. Connect to pin 5.
Digital Supply, 3.3V ±5%. Bypass DV
Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
Chip Select Input. Drive CS low to enable the serial interface. When CS is high DOUT is high impedance. In
external clock mode SSTRB is high impedance when CS is high.
Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.
Analog Ground. Connect to pin 3.
Analog Input
DD
DD
to DGND (pin 14) with a 0.1µF capacitor.
to AGND (pin 3) with a 0.1µF capacitor.
FUNCTION
Pin Description
7