LTC1197LCMS8 Linear Technology, LTC1197LCMS8 Datasheet - Page 23
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LTC1197LCMS8
Manufacturer Part Number
LTC1197LCMS8
Description
IC ADC 10BIT 250KHZ W/SD 8-MSOP
Manufacturer
Linear Technology
Datasheet
1.LTC1197CS8PBF.pdf
(28 pages)
Specifications of LTC1197LCMS8
Number Of Bits
10
Sampling Rate (per Second)
250k
Data Interface
MICROWIRE™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
25mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC1197LCMS8
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC1197LCMS8
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC1197LCMS8#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1199 and parallel port micro-
processors. Normally, the CS, CLK and D
be generated on three port lines and the D
on a fourth port line. This works very well. However, we
will demonstrate here an interface with the D
of the LTC1199 tied together as described in the
SERIAL INTERFACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1199 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
DATA (D
TYPICAL APPLICATIO S
ANALOG
INPUTS
IN
/D
OUT
CLK
CS
CLK AND BEFORE THE 4TH FALLING CLK
)
R2
R3
D
AS AN INPUT AFTER THE 4TH RISING
MSB
OUT
B9
B1
LTC1199
from LTC1199 Stored in 8051 RAM
START
LSB
8051 P1.2 OUTPUTS DATA
B8
B0
8051 P1.2 RECONFIGURED
1
D
TO LTC1199
B7
CLK
0
OUT
D
SGL/
CS
DIFF
IN
2
B6
0
ODD/
SIGN
MUX ADDRESS
B5
0
A/D RESULT
3
DUMMY
U
B4
0
B3
4
0
IN
1197/99 TA07
OUT
P1.4
P1.3
P1.2
B2
signals would
0
LTC1199 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
IN
signal read
and D
8051
1197/99 TA06
OUT
B9
B8
LABEL
LOOP 1
LOOP
B7
MNEMONIC
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
CLR
CLR
RLC
MOV
RRC
RRC
MOV
SETB
LTC1199 SENDS A/D RESULT
B6
BACK TO 8051 P1.2
B5
LTC1197/LTC1197L
LTC1199/LTC1199L
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #0AH
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
C, P1.2
P1.3
P1.3
A
A
C, P1.2
A
A
R3, A
P1.4
OPERAND
B4
B3
COMMENTS
D
Make sure CS is high
CS goes low
Load counter
Rotate D
CLK goes low
Output D
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into ACC
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
Read data bit into Carry
CLK goes high
CLK goes low
Clear ACC
Rotate data bit from Carry to
ACC
Read data bit into Carry
Rotate right into ACC
Rotate right into ACC
Store LSBs in R3
CS goes high
IN
word for LTC1199
B2
IN
IN
bit into Carry
bit into Carry
B1
23
B0
1197/99 TA08