LTC2420IS8#TR Linear Technology, LTC2420IS8#TR Datasheet - Page 16

• Manufacturer Part Number: LTC2420IS8#TR
• Description: IC ADC 20BIT MICROPOWER 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC2420IS8#TR

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
(EXTERNAL)
LTC2420
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
16
SDO
SCK
CS
Hi-Z
CONVERSION
TEST EOC
U
TEST EOC
SLEEP
U
Hi-Z
Figure 6. External Serial Clock, Single Cycle Operation
BIT 23
W
EOC
BIT 22
–0.12V
REF
U
0.1V TO V
TO 1.12V
BIT 21
SIG
1 F
2.7V TO 5.5V
V
REF
V
REF
CC
IN
BIT 20
EXR
V
V
V
GND
CC
REF
IN
LTC2420
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground (Pin 4), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and EOC
= 0 once the conversion enters the low power sleep state.
On the falling edge of EOC, the conversion result is loaded
BIT 19
MSB
SDO
SCK
DATA OUTPUT
CS
F
O
BIT 18
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 4
CC
exceeds 2.2V. The level
LSB
BIT 0
20
CONVERSION
Hi-Z
TEST EOC
2420 F06