LTC2411CMS Linear Technology, LTC2411CMS Datasheet - Page 25

• Manufacturer Part Number: LTC2411CMS
• Description: IC A/D CONV 24BIT MICRPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2411CMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Figure 16. Offset Error vs Common Mode Voltage
(V
( R
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/ C) are
used for the external source impedance seen by IN
IN
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
in a small offset shift. A 100 source resistance will create
a 0.1 V typical and 1 V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2411/LTC2411-1 sample the
differential reference pins REF
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
INCM
–
IN
, the expected drift of the dynamic current, offset and
= R
= IN
SOURCEIN +
+
–10
–20
–30
–40
–50
= IN
50
40
30
20
10
0
0
A: R
B: R
C: R
D: R
B
C
D
E
G
–
A
F
) and Input Source Resistance Imbalance
0.5
– R
IN
IN
IN
IN
1
= +400
= +200
= +100
U
= 0
SOURCEIN –
1.5
V
REF
REF
IN
F
T
R
C
CC
O
A
IN
SOURCEIN
+
2
= GND
= 25 C
V
+
= IN
= 10 F
U
–
= 5V
INCM
= 5V
= GND
2.5
) for Large C
–
= V
+
(V)
– = 500
and REF
3 3.5
INCM
E: R
F: R
G: R
W
IN
IN
IN
4
= –200
= –100
= –400
–
IN
4.5
2411 F16
transfering small
Values (C
5
U
IN
+
1 F)
and
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sam-
pling charge and the external source resistance will see a
quasi constant reference differential impedance. For the
LTC2411, when F
notch), the typical differential reference resistance is
3.9M which will generate a gain error of approximately
0.13ppm for each ohm of source resistance driving REF
or REF
notch), the typical differential reference resistance is
4.68M which will generate a gain error of approximately
0.11ppm for each ohm of source resistance driving REF
or REF
used (F
tance is 4.29M
approximately 0.12ppm for each ohm of source resis-
tance driving REF
external oscillator with a frequency f
version clock operation), the typical differential reference
resistance is 0.60 • 10
resistance drving REF
10
resistance on the two reference pins is additive with
respect to this gain error. The typical FS errors for various
combinations of source resistance seen by the REF
REF
these pins are shown in Figures 17 and 18. Typical – FS
errors are similar to + FS errors with opposite polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
For LTC2411, when F
notch), every 100 of source resistance driving REF
–6
–
• f
pins and external capacitance C
REF
–
–
O
. When F
. For the LTC2411-1, when internal oscillator is
EOSC
= LOW), the typical differential reference resis-
< 0.01 F), the voltage on the sampling capacitor
REF
ppm gain error. The effect of the source
will deteriorate the converter offset and
LTC2411/LTC2411-1
O
O
+
which will generate a gain error of
= HIGH (internal oscillator and 50Hz
= LOW (internal oscillator and 60Hz
or REF
O
12
= LOW (internal oscillator and 60Hz
+
/f
or REF
EOSC
–
. When F
–
and each ohm of source
will result in 0.823 •
EOSC
O
REF
is driven by an
REF
(external con-
connected to
> 0.01 F)
25
+
and
+
or
+
+