LTC1402IGN Linear Technology, LTC1402IGN Datasheet - Page 13

• Manufacturer Part Number: LTC1402IGN
• Description: IC ADC 12BIT 2.2MSPS SHDN 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC1402IGN

• Number Of Bits: 12
• Sampling Rate (per Second): 2.2M
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 150mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a voltage span that equals
the difference between the voltage at the reference buffer
output V
ground AGND2 at Pin 6. The external reference voltage
may have any value between 2V and 5V. The internal ADC
is referenced to these two points. If you use an external
reference, tie the GAIN (Pin 7) to AV
the internal reference, and connect the external reference
between V
If you cut the reference voltage in half by halving the gain
of the reference buffer with the GAIN (Pin 7) tied to V
(Pin 5), the input span also cuts in half. In bipolar mode,
the differential input range changes from 2.048V to
mode, the differential input range changes from 0V-
4.096V to 0V-2.048V, for the same reference cut in half.
Note that in both unipolar and bipolar modes, the input
range pivots around 0V with changing reference voltage.
AGND2 (Pin 6) has no direct effect on the ADC offset
voltage, it only affects input voltage span. Any external
offsetting voltages must be applied through the A
A
SEVERAL LTC1402 ADCs MAY SHARE ONE
EXTERNAL REFERENCE
Figure 8 shows how several ADCs can share a single
common external reference. The V
(Pin 6) of several LTC1402 ADCs can be tied together to
share the same external reference in a data acquisition
system. Tie GAIN (Pin 7) to AV
1.024V, when the reference is cut in half. In unipolar
IN
–
inputs, as shown in Figure 10b.
REF
REF
– 20
– 30
– 40
– 50
– 60
–10
–70
at Pin 5, and the voltage at the reference
0
(Pin 5) and AGND2 (Pin 6).
0.1
Figure 7. CMRR vs Input Frequency
U
1
FREQUENCY (MHz)
INFORMATION
U
10
DD
REF
at each ADC to disable
W
DD
100
(Pin 5) and AGND2
(Pin 1) to disable
1402 F07
1000
U
IN
+
and
REF
all the internal references. When AGND2 (Pin 6) is tied to
the external ground plane, it sources 2.7mA 30% typi-
cally; approximately 2mA are sourced through an internal
equivalent 2k resistance tied to the V
and the remaining 0.7mA supply the internal reference
ground. The V
same 2k tied to AGND2 (Pin 6). When you bus a common
reference voltage to several LTC1402 ADCs, you need to
keep PC board track resistance low to avoid reference
voltage attenuation at each ADC. For example, 0.5
track resistance to Pins 5 or 6 causes 0.025% of reference
voltage and input range reduction. Figure 8 shows op-
tional buffer amplifiers at each ADC to eliminate resistive
voltage drops from the common external reference to each
ADC. Figure 8 shows 10 F bypass capacitors tied to the
common analog ground plane, at V
(Pin 6), wired closely to each ADC to eliminate crosstalk of
internal ADC glitch currents from one ADC to another. The
10 F bypass capacitors are recommended whether you
drive Pins 5 and 6 with amplifiers, or with copper traces
5V
LT1634AI-4.096
10k
4.096V
0.1 F
Figure 8. Several LTC1402 ADCs Can Share a Single
External Reference
1k
REF
(Pin 5) equivalent input resistance is the
1/2 LT1368CS8
1/2 LT1368CS8
1/2 LT1368CS8
1/2 LT1368CS8
6
5
2
3
6
5
2
3
–
+
–
+
–
+
–
+
–5V
–5V
5V
5V
8
4
8
4
7
10 F
10 F
7
1
10 F
1
10 F
ANALOG
ANALOG
INPUTS
INPUTS
REF
REF
(Pin 5) and AGND2
5V
5V
(Pin 5) at 4.096V
3
2
5
6
7
3
2
5
6
7
LTC1402
A
A
V
AGND2
GAIN
A
A
V
AGND2
GAIN
IN
IN
REF
IN
IN
REF
+
–
+
–
LTC1402
LTC1402
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•
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1402 F08
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