LTC2351HUH-12#TRPBF Linear Technology, LTC2351HUH-12#TRPBF Datasheet - Page 17

• Manufacturer Part Number: LTC2351HUH-12#TRPBF
• Description: IC ADC 12BIT 1.5MSPS 32-QFN
• Manufacturer: Linear Technology

Specifications of LTC2351HUH-12#TRPBF

• Number Of Bits: 12
• Sampling Rate (per Second): 1.5M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 16.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2351-12 has a 3-wire SPI (Serial Peripheral
Interface) interface. The SCK and CONV inputs and SDO
output implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed V
of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC2351-12
until the following 96 SCK rising edges have occurred. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC2351-12 and then buffer this
signal to drive the frame sync input of the processor serial
port. It is good practice to drive the LTC2351-12 CONV
input fi rst to avoid digital noise interference during the
sample-to-hold transition triggered by CONV at the start
of conversion. It is also good practice to keep the width
of the low portion of the CONV signal greater than 15ns
to avoid introducing glitches in the front end of the ADC
just before the sample-and-hold goes into Hold mode at
the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine waves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. The SCK and CONV inputs
should be driven fi rst, with digital buffers used to drive
the serial port interface. Also note that the master clock
in the DSP may already be corrupted with jitter, even if it
comes directly from the DSP crystal. Another problem with
high speed processor clocks is that they often use a low
cost, low speed crystal (i.e., 10MHz) to generate a fast,
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. A detailed description
but jittery, phase-locked-loop system clock (i.e., 40MHz).
The jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
The Typical Application fi gure on page 20 shows a circuit
for level-shifting and squaring the output from an RF signal
generator or other low-jitter source. A single D-type fl ip fl op
is used to generate the CONV signal to the LTC2351-12.
Re-timing the master clock signal eliminates clock jitter
introduced by the controlling device (DSP , FPGA, etc.)
Both the inverter and fl ip fl op must be treated as analog
components and should be powered from a clean analog
supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out up to
six sets of 12 data bits, with the MSB sent fi rst. A simple
approach is to generate SCK to drive the LTC2351-12 fi rst
and then buffer this signal with the appropriate number of
inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the serial data output (SDO) into your processor
serial port. The 12-bit serial data will be received in six
16-bit words with 96 or more clocks per frame sync. If
fewer than 6 channels are selected by SEL0–SEL2 for
conversion, then 16 clocks are needed per channel to
convert the analog inputs and read out the resulting data
after the next convert pulse. It is good practice to drive the
LTC2351-12 SCK input fi rst to avoid digital noise interfer-
ence during the internal bit comparison decision by the
internal high speed comparator. Unlike the CONV input,
the SCK input is not sensitive to jitter because the input
signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends out
up to six sets of 12 bits in the output data stream after the
third rising edge of SCK after the start of conversion with
LTC2351-12
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