LTC1419AISW Linear Technology, LTC1419AISW Datasheet - Page 7

• Manufacturer Part Number: LTC1419AISW
• Description: IC A/D CONV 14BIT SAMPLNG 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1419AISW

• Number Of Bits: 14
• Sampling Rate (per Second): 800k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 240mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
CONVERSION DETAILS
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
TEST CIRCUITS
+A
–A
DBN
IN
IN
SAMPLE
SAMPLE
(A) Hi-Z TO V
1k
+V
Figure 1. Simplified Block Diagram
DAC
Load Circuits for Access Timing
–V
DAC
HOLD
HOLD
OH
U
–C
+C
–C
+C
SAMPLE
SAMPLE
DAC
DAC
C
L
INFORMATION
U
SAR
ZEROING SWITCHES
14
DBN
+
–
W
HOLD
HOLD
COMP
LATCHES
OUTPUT
(B) Hi-Z TO V
5V
1k
C
1419 F01
U
L
O
1419 TC01
•
•
•
D13
D0
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the + A
nected to the sample-and-hold capacitors (C
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the C
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the + A
The SAR contents (a 14-bit data word) which represents
the difference of + A
output latches.
DYNAMIC PERFORMANCE
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
DBN
Load Circuits for Output Float Delay
(A) V
1k
SAMPLE
OH
TO Hi-Z
IN
and – A
capacitors to ground, transferring
100pF
IN
IN
IN
and – A
are loaded into the 14-bit
and – A
DBN
IN
IN
LTC1419
(B) V
inputs are con-
input charges.
SAMPLE
OL
5V
TO Hi-Z
1k
100pF
) dur-
1419 TC02
1419fb
7