LTC1748IFW Linear Technology, LTC1748IFW Datasheet - Page 9
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LTC1748IFW
Manufacturer Part Number
LTC1748IFW
Description
IC ADC SMPL 14BIT 80MSPS 48TSSOP
Manufacturer
Linear Technology
Datasheet
1.LTC1748CFW.pdf
(20 pages)
Specifications of LTC1748IFW
Number Of Bits
14
Sampling Rate (per Second)
80M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
1.55W
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1748IFW#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
SENSE (Pin 1): Reference Sense Pin. Ground selects 1V.
V
applied to the SENSE pin selects an input range of V
V
Bypass to ground with 4.7 F ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power
Ground.
A
A
V
with 1 F ceramic chip capacitors at Pin 8 and Pin 18.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1 F ceramic chip capacitor. Do not connect to
Pin 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1 F ceramic chip capacitor, to Pin 14 with a 4.7 F ceramic
capacitor and to ground with 1 F ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1 F ceramic chip capacitor, to Pin 11 with a 4.7 F ce-
ramic capacitor and to ground with 1 F ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1 F ceramic chip capacitor. Do not connect to
Pin 11.
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
1.6V is the largest valid input range.
DD
CM
IN
IN
DD
U
+
–
(Pin 2): 2.35V Output and Input Common Mode Bias.
(Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
selects 1.6V. Greater than 1V and less than 1.6V
(Pin 4): Positive Differential Analog Input.
(Pin 5): Negative Differential Analog Input.
U
–4
–2
–6
–8
8
6
4
2
0
– 50
Offset and Gain Error
vs Temperature
U
–30
–10
W
GAIN ERROR
TEMPERATURE ( C)
10
U
30
OFFSET ERROR
50
70
1748 G35
90
SENSE
,
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on the
positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1 F
ceramic for single-ended ENCODE signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z. OE should not exceed the
votlage on OV
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs.
OV
ers. Bypass to ground with 0.1 F ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
DD
(Pins 32, 43): Positive Supply for the Output Driv-
300
290
280
270
260
250
240
230
0
Supply Current vs Sample Rate
T
A
= 25 C
DD
20
.
SAMPLE RATE (Msps)
40
60
80
1748 G32
100
LTC1748
1748fa
9