LTC2173CUKG-14#TRPBF Linear Technology, LTC2173CUKG-14#TRPBF Datasheet - Page 24

• Manufacturer Part Number: LTC2173CUKG-14#TRPBF
• Description: IC ADC 14BIT 80MSPS QUAD 52QFN
• Manufacturer: Linear Technology

Specifications of LTC2173CUKG-14#TRPBF

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Number Of Converters: 4
• Power Dissipation (max): 454mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2175-14/
LTC2174-14/LTC2173-14
APPLICATIONS INFORMATION
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
A
(2V RANGE)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
<–1.000000V
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
24
IN
+
– A
IN
–
(OFFSET BINARY)
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
D13-D0
(2’s COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D13-D0
and all other bits. The FR and DCO outputs are not affected.
The output randomizer is enabled by serially programming
mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the test
patterns override all other formatting modes: 2’s comple-
ment and randomizer.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
power or enable in-circuit testing. When disabled the com-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SDI (parallel programming mode). The amount
of time required to recover from sleep mode depends
on the size of the bypass capacitors on V
REFL. For the suggested values in Figure 8, the A/D will
stabilize after 2ms.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wakeup than from sleep
REF
, REFH, and
21754314f