AD7706BRU-REEL7 Analog Devices Inc, AD7706BRU-REEL7 Datasheet - Page 10

• Manufacturer Part Number: AD7706BRU-REEL7
• Description: IC ADC 16BIT 3CH 16-TSSOP T/R
• Manufacturer: Analog Devices Inc

Specifications of AD7706BRU-REEL7

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-AD7706EBZ - BOARD EVALUATION FOR AD7706

AD7705/AD7706
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
AD7705
SCLK
MCLK IN
MCLK OUT MCLK OUT
CS
RESET
AIN2(+)
AIN1(+)
AIN1(−)
REF IN(+)
REF IN(−)
AIN2(−)
DRDY
DOUT
MCLK OUT
MCLK IN
AIN2(+)
AIN1(+)
AIN1(–)
RESET
SCLK
Mnemonic
Figure 3. AD7705 Pin Configuration
CS
1
2
3
4
5
6
7
8
AD7706
SCLK
MCLK IN
CS
RESET
AIN1
AIN2
COMMON
REF IN(+)
REF IN(−)
AIN3
DRDY
DOUT
(Not to Scale)
AD7705
TOP VIEW
Description
Serial Clock. An external serial clock is applied to the Schmitt-triggered logic input to access serial
data from the AD7705/AD7706. This serial clock can be a continuous clock with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information
transmitted to the AD7705/AD7706 in smaller batches of data.
Master Clock Signal. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the Pin MCLK IN and Pin MCLK OUT. Alternatively, the MCLK IN
pin can be driven with a CMOS-compatible clock with the MCLK OUT pin left unconnected. The parts
can be operated with clock frequencies in the range of 500 kHz to 5 MHz.
When the master clock for these devices is a crystal/resonator, the crystal/resonator is connected
between Pin MCLK IN and Pin MCLK OUT. If an external clock is applied to Pin MCLK IN, Pin MCLK OUT
provides an inverted clock signal. This clock can be used to provide a clock source for external
circuitry and is capable of driving 1 CMOS load. If the user does not require this clock externally, Pin
MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the part does
not unnecessarily burn power driving capacitive loads on Pin MCLK OUT.
Chip Select. Active low logic input used to select the AD7705/AD7706. With this input hardwired low,
the AD7705/AD7706 can operate in its 3-wire interface mode with Pin SCLK, Pin DIN, and Pin DOUT
used to interface to the device. The CS pin can be used to select the device communicating with the
AD7705/AD7706.
Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients,
digital filter, and analog modulator of the parts to power-on status.
Positive Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 1 for AD7706.
Positive Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. Channel 2 for AD7706.
Negative Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. COMMON input for
AD7706 with Channel 1, Channel 2, and Channel 3 referenced to this input.
Reference Input. Positive input of the differential reference input to the AD7705/AD7706. The reference
input is differential with the provision that REF IN(+) must be greater than REF IN(−).
REF IN(+) can lie anywhere between V
Reference Input. Negative input of the differential reference input to the AD7705/AD7706. The
REF IN(−) can lie anywhere between V
Negative Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 3 for AD7706.
Logic Output. A logic low on this output indicates that a new output word is available from the
AD7705/AD7706 data register. The DRDY pin returns high upon completion of a read operation of a
full output word. If no data read has taken place between output updates, the DRDY line returns high
for 500 × t
neither be attempted nor in progress to avoid reading from the data register as it is being updated.
The DRDY line returns low after the update has taken place. DRDY is also used to indicate when the
AD7705/AD7706 has completed its on-chip calibration sequence.
Serial Data Output. Serial data is read from the output shift register on the part. The output shift
register can contain information from the setup register, communication register, clock register, or
data register, depending on the register selection bits of the communication register.
16
15
14
13
12
11
10
9
GND
V
DIN
DOUT
DRDY
AIN2(–)
REF IN(–)
REF IN(+)
DD
CLK IN
cycles prior to the next output update. While DRDY is high, a read operation should
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DD
DD
and GND, provided that REF IN(+) is greater than REF IN(−).
and GND.
MCLK OUT
COMMON
MCLK IN
RESET
SCLK
Figure 4. AD7706 Pin Configuration
AIN1
AIN2
CS
1
2
3
4
5
6
7
8
(Not to Scale)
TOP VIEW
AD7706
16
15
14
13
12
11
10
9
GND
V
DIN
DOUT
DRDY
AIN3
REF IN(–)
REF IN(+)
DD