AD7323BRUZ Analog Devices Inc, AD7323BRUZ Datasheet - Page 9

• Manufacturer Part Number: AD7323BRUZ
• Description: IC ADC 12BIT+ SAR 4CHAN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7323BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Number Of Converters: 1
• Power Dissipation (max): 17mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 500kSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7323CBZ - BOARD EVALUATION FOR AD7323CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3, 15
4
5
6
7, 8, 9, 10
11
12
13
14
16
Mnemonic
CS
DIN
DGND
AGND
REFIN/OUT
V
V
V
V
V
DOUT
SCLK
SS
IN
DD
CC
DRIVE
0 to V
IN
3
Description
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7323 and frames the serial data transfer.
Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Registers section).
Digital Ground. Ground reference point for all digital circuitry on the AD7323. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Analog Ground. Ground reference point for all analog circuitry on the AD7323. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7323. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor
should be placed on the reference pin (see the Reference section). Alternatively, the internal reference
can be disabled and an external reference applied to this input. On power-up, the external reference
mode is the default condition.
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the ADD1 and ADD0 channel
address bits in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs (see Table 10).
The configuration of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0,
in the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a 2.5 V reference voltage is used (see the Registers section).
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7323.
This supply should be decoupled to AGND.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different from that at
V
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data.
The data stream consists of a leading zero, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7323. This clock is also used as the clock source for the conversion process.
CC
, but it should not exceed V
REFIN/OUT
DGND
AGND
V
V
V
DIN
CS
IN
IN
Figure 3. Pin Configuration
SS
0
1
1
2
3
4
5
6
7
8
Rev. A | Page 9 of 36
(Not to Scale)
TOP VIEW
AD7323
CC
by more than 0.3 V.
15
14
13
12
11
10
16
9
SCLK
DGND
DOUT
V
V
V
V
V
DRIVE
CC
DD
IN
IN
2
3
AD7323