AD7495AR-REEL7 Analog Devices Inc, AD7495AR-REEL7 Datasheet - Page 11
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AD7495AR-REEL7
Manufacturer Part Number
AD7495AR-REEL7
Description
IC ADC 12BIT SRL LP W/REF 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD7475ARMZ-REEL7.pdf
(24 pages)
Specifications of AD7495AR-REEL7
Rohs Status
RoHS non-compliant
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
10.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
TERMINOLOGY
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a point ½ LSB below the
first code transition, and full scale, a point ½ LSB above the last
code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111. . . 110) to
(111. . . 111) from the ideal (that is, V
offset error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode on the
13
track-and-hold acquisition time is the minimum time required
for the track-and-hold amplifier to remain in track mode for its
output to reach and settle to within 0.5 LSB of the applied input
signal, given a step change to the input signal.
Signal-to-Noise and Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the analog-to-digital converter (ADC). The signal is
the rms amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(f
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical SINAD ratio
for an ideal N-bit converter with a sine wave input is given by
For a 12-bit converter, the SINAD is 74 dB.
S
/2), excluding dc. The ratio is dependent on the number of
th
SCLK rising edge (see the Serial Interface section). The
Signal
to
(
Noise
+
Distortion
) (
=
REF
. 6
− 1.5 LSB) after the
02
N
+
. 1
76
)
dB
Rev. B | Page 11 of 24
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7475/AD7495, THD is defined as
where V
V
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in
the ADC output spectrum (up to f
the rms value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried in
the noise floor, it is a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7475/AD7495 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. Like THD, intermodulation distortion is
calculated as the rms sum of the individual distortion products
to the rms amplitude of the sum of the fundamentals, expressed
in dBs.
4
, V
THD
5
, and V
1
is the rms amplitude of the fundamental and V
( )
dB
6
=
are the rms amplitudes of the second through the
20
log
V
2
2
+
V
3
2
+
V
S
V
/2 and excluding dc) to
1
4
2
+
AD7475/AD7495
V
5
2
+
V
6
2
2
, V
3
,