AD7687BRMZ Analog Devices Inc, AD7687BRMZ Datasheet - Page 19

• Manufacturer Part Number: AD7687BRMZ
• Description: IC ADC 16BIT 250KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7687BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 12.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.3V To 5.5V
• Supply Voltage Range - Digital: 1.8V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7687CBZ - BOARD EVALUATION FOR AD7687
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 37 and the
corresponding timing is given in Figure 38.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7687 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
ACQUISITION
SDI = 1
SDO
CNV
SCK
CONVERSION
t
CONV
t
CNVH
Figure 38. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
1
t
t
HSDO
DSDO
Rev. A | Page 19 of 28
D15
t
2
CYC
ACQUISITION
D14
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
If multiple AD7687s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
t
3
VIO
ACQ
SDI
t
SCKL
AD7687
t
Figure 37. CS Mode 3-Wire with BUSY Indicator
SCKH
15
CNV
SCK
Connection Diagram (SDI High)
t
SCK
SDO
16
D1
VIO
17
D0
47k Ω
CONVERT
DATA IN
IRQ
CLK
t
DIGITAL HOST
DIS
AD7687