AD7710AR Analog Devices Inc, AD7710AR Datasheet - Page 17

• Manufacturer Part Number: AD7710AR
• Description: IC ADC 24BIT DIFF INP 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7710AR

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Features: 24-Bit, Signal Conditioning W/2 Diff. In Ch.
• No. Of Channels: 2
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REV. G
USING THE AD7710
SYSTEM DESIGN CONSIDERATIONS
The AD7710 operates differently from successive approxima-
tion ADCs or integrating ADCs. Because it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter, and the output can be
read at any time, either synchronously or asynchronously.
Clocking
The AD7710 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be connected
between MCLK IN and MCLK OUT, in which case the clock
circuit will function as a crystal-controlled oscillator. For lower
clock frequencies, a ceramic resonator may be used instead of
the crystal. For these lower frequency oscillators, external
capacitors may be required on either the ceramic resonator or
on the crystal.
The input sampling frequency, the modulator sampling fre-
quency, the –3 dB frequency, the output update rate, and the
calibration time are all directly related to the master clock fre-
quency f
of 2 will halve the above frequencies and update rate and will
double the calibration time.
The current drawn from the DV
related to f
DV
AV
System Synchronization
If multiple AD7710s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the SYNC input resets the filter and
places the AD7710 into a consistent, known state. A common
signal to the AD7710s’ SYNC inputs will synchronize their
operation. This would typically be done after each AD7710 has
performed its own calibration or has had calibration coefficients
loaded to it.
The SYNC input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DV
ating internally before the DV
operating level, 4.75 V. With a low DV
AD7710’s internal digital filter logic does not operate correctly.
Thus, the AD7710 may have clocked itself into an incorrect
operating condition by the time that DV
rect level. The digital filter will be reset upon issue of a calibra-
tion command (whether it is self-calibration, system calibration,
or background calibration) to the AD7710. This ensures correct
operation of the AD7710. In systems where the power-on
default conditions of the AD7710 are acceptable, and no cali-
bration is performed after power-on, issuing a SYNC pulse to
the AD7710 will reset the AD7710’s digital filter logic. An R, C
on the SYNC line, with R, C time constant longer than the
DV
DD
DD
DD
DD
power supply.
current but will not affect the current drawn from the
power-on time, will perform the SYNC function.
) is very long. In such cases, the AD7710 will start oper-
CLK IN
CLK IN
. Reducing the master clock frequency by a factor
. Reducing f
CLK IN
DD
DD
line has reached its minimum
by a factor of 2 will halve the
power supply is also directly
DD
DD
has reached its cor-
voltage, the
–17–
Accuracy
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7710 achieves excellent
linearity by the use of high quality, on-chip silicon dioxide
capacitors, which have a very low capacitance/voltage coefficient.
The device also achieves low input drift through the use of chopper
stabilized techniques in its input stage. To ensure excellent perfor-
mance over time and temperature, the AD7710 uses digital
calibration techniques that minimize offset and gain error.
Autocalibration
Autocalibration on the AD7710 removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch, or bipolar/unipolar
input range. However, if the AD7710 is in its background cali-
bration mode, these changes are all automatically taken care of
(after the settling time of the filter has been allowed for).
The AD7710 offers self-calibration, system calibration, and
background calibration facilities. For calibration to occur on the
selected channel, the on-chip microcontroller must record the
modulator output for two different input conditions. These are
zero-scale and full-scale points. With these readings, the micro-
controller can calculate the gain slope for the input to output
transfer function of the converter. Internally, the part works
with a resolution of 33 bits to determine its conversion result of
either 16 bits or 24 bits.
The AD7710 also provides the facility to write to the on-chip
calibration registers, and, in this manner, the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value that is subtracted from all conversion
results, while the full-scale calibration register contains a value
that is multiplied by all conversion results. The offset calibration
coefficient is subtracted from the result prior to the multiplica-
tion by the full-scale coefficient. In the first three modes out-
lined here, the DRDY line indicates that calibration is complete
by going low. If DRDY is low before (or goes low during) the
calibration command, it may take up to one modulator cycle
before DRDY goes high to indicate that calibration is in
progress. Therefore, DRDY should be ignored for up to one
modulator cycle after the last bit of the calibration command is
written to the control register.
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (that is, AIN(+) = AIN(–) = V
and the full-scale point is V
determined by converting an internal shorted inputs node. The
full-scale coefficient is determined from the span between this
shorted inputs conversion and a conversion on an internal V
node. The self-calibration mode is invoked by writing the appro-
priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the
control register. In this calibration mode, the shorted inputs
node is switched in to the modulator first and a conversion is
REF
. The zero-scale coefficient is
AD7710
BIAS
REF
)