MAX11203EEE+T Maxim Integrated Products, MAX11203EEE+T Datasheet - Page 9

• Manufacturer Part Number: MAX11203EEE+T
• Description: IC ADC 16BIT SPI/SRL 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX11203EEE+T

• Number Of Bits: 16
• Sampling Rate (per Second): 10
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 667mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX11203/MAX11213 are ultra-low-power (< 300FA
active), high-resolution, low-speed, serial-output ADCs.
These ADCs provide the highest resolution per unit power
in the industry, and are optimized for applications that
require very high dynamic range with low power such
as sensors on a 4mA to 20mA industrial control loop.
Optional input buffers provide isolation of the signal inputs
from the switched capacitor sampling network, allow-
ing the devices to be used with very high impedance
sources without compromising available dynamic range.
The devices provide a high-accuracy internal oscillator,
which requires no external components. When used with
the specified data rates, the internal digital filter provides
more than 144dB rejection of 50Hz or 60Hz line noise. The
devices are highly configurable using the SPI interface
and include four GPIOs for external mux control.
The devices accept two analog inputs (AINP, AINN) in
buffered or unbuffered mode. The input buffer isolates
Table 1. Continuous Conversion with SCYCLE Bit = 0
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock
frequency to 2.048MHz and the input sampling frequency to 204.8kHz.
Table 2. Single-Cycle Conversion with SCYCLE Bit = 1
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock
frequency to 2.048MHz and the input sampling frequency to 204.8kHz.
RATE[2:0]
Sigma ADCs with Programmable Gain and GPIO
RATE[2:0]
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
000
001
010
011
100
101
110
111
100
101
110
111
SINGLE-CYCLE DATA RATE*
LINEF = 0
LINEF = 0
_______________________________________________________________________________________
120
2.5
10
15
30
60
1
5
120
240
480
60
DATA RATE* (sps)
Detailed Description
(sps)
LINEF = 1
0.833
LINEF = 1
2.08
4.17
8.33
12.5
100
25
50
100
200
400
50
Analog Inputs
NFR (BITS)
BIPOLAR
BIPOLAR NFR
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
(BITS)
16.0
16.0
16.0
16.0
BIPOLAR
the inputs from the capacitive load presented by the
modulator, allowing for high source-impedance analog
transducers. The value of the SIGBUF bit in the CTRL1
register determines whether the input buffer is enabled
or disabled. See Table 12.
The modulator input range is programmable for bipolar
(-V
U/B bit in the CTRL1 register configures the MAX11203/
MAX11213 for unipolar or bipolar transfer functions. See
Table 12.
The devices incorporate a highly stable internal oscillator
that provides the system clock. The system clock runs
the internal state machine and is trimmed to 2.4576MHz
or 2.048MHz. The internal oscillator clock is divided
down to run the digital and analog timing. The LINEF bit
in the CTRL1 register determines the internal oscillator
frequency. See Tables 10 and 12. Set LINEF = 0 to select
the 2.4576MHz oscillator and LINEF = 1 to select the
ENOB
(BITS)
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
BIPOLAR
REF
ENOB
(BITS)
16.0
16.0
16.0
16.0
to +V
UNIPOLAR
NFR (BITS)
REF
NFR (BITS)
UNIPOLAR
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
) or unipolar (0 to V
16.0
16.0
16.0
16.0
ENOB (BITS)
UNIPOLAR
UNIPOLAR
Input Voltage Range
ENOB
(BITS)
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
REF
System Clock
) ranges. The
OUTPUT
OUTPUT
(µV
(µV
NOISE
NOISE
0.21
0.27
0.39
0.57
0.74
1.03
1.45
2.21
0.74
1.03
1.45
2.21
RMS
RMS
)
)
9