MAX11212AEUB+ Maxim Integrated Products, MAX11212AEUB+ Datasheet - Page 10

• Manufacturer Part Number: MAX11212AEUB+
• Description: IC ADC 18BIT SRL 120SPS 10UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX11212AEUB+

• Number Of Bits: 18
• Sampling Rate (per Second): 120
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 444mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Conversion Rate: 120 SPs
• Resolution: 18 bit
• Interface Type: SPI
• Voltage Reference: 3.6 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 444 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.7 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
The MAX11212 indicates conversion data availabil-
ity as well as allows the retrieval of data through the
RDY/DOUT output. The RDY/DOUT output idles at the
value of the last bit read unless a 25th SCLK pulse is
provided, causing RDY/DOUT to idle high. RDY/DOUT is
pulled low when the conversion data is available.
Figure 1 shows the timing diagram for the data read.
Once a low is detected on RDY/DOUT, clock pulses at
SCLK clock out the data. Data is shifted out MSB first
and is in binary two’s complement format. Once all the
data has been shifted out, a 25th SCLK is required to
pull the RDY/DOUT output back to the idle high state.
See Figure 2.
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Figure 1. Timing Diagram for Data Read After Conversion
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
SCLK
SCLK
RDY/DOUT
RDY/DOUT
CONVERSION IS DONE
CONVERSION IS DONE
DATA IS AVAILABLE
DATA IS AVAILABLE
_____________________________________________________________________________________
Data Read Following Every Conversion
t
5
t
3
1
1
D17
D17
2
2
D16
D16
t
1
t
3
3
2
t
7
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
To initiate self-calibration at the end of a data read,
provide a 26th SCLK pulse. After reading the 16 bits of
conversion data, a 25th positive edge on SCLK pulls
the RDY/DOUT output back high, indicating end of data
read. Provide a 26th SCLK pulse to initiate a self-calibra-
tion routine starting on the falling edge of the 26th SCLK.
A subsequent falling edge of RDY/DOUT indicates data
availability at the end of calibration. The timing is illus-
trated in Figure 3.
t
4
24
24
0
0
25TH SLK RISING EDGE
25
PULLS RDY/DOUT
Data Read Followed by Self-Calibration
HIGH
CONVERSION IS DONE
CONVERSION IS DONE
DATA IS AVAILABLE
DATA IS AVAILABLE
t
6