MAX194BCWE+ Maxim Integrated Products, MAX194BCWE+ Datasheet - Page 17

• Manufacturer Part Number: MAX194BCWE+
• Description: IC ADC 14BIT 85KSPS SHTDN 16SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX194BCWE+

• Number Of Bits: 14
• Sampling Rate (per Second): 85k
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 80mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18. Timing Diagram for Circuit of Figure 17
Figure 19. MAX194 Connection to QSPI Processor Clocking
Data Out with SCLK Between Conversions
MicroWire is a trademark of National Semiconductor Corp.
START
QSPI
GPT
CS, CONV
IC3
DOUT
DATA LATCHED:
EOC
CLK
PCS0
MISO
SCK
OC3
OC2
IC1
1.3 s
14-Bit, 85ksps ADC with 10µA Shutdown
______________________________________________________________________________________
t
DV
B13 FROM PREVIOUS
74HC32
CONVERSION
CS
SCLK
DOUT
BP/UP/SHDN
EOC
RESET
CONV
MAX194
CLK
B13
t
CD
1.7MHz
B12
Data is clocked out of the MAX194 on CLK’s falling
edge and can be clocked into the µP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard MicroWire™: Hitachi H8), the maximum
CLK rate is given by:
where t
and t
If clocking data in on the falling edge (CPOL = 0,
CPHA = 1), the maximum CLK rate is given by:
Do not exceed the maximum CLK frequency given in
the Electrical Characteristics table. To clock data in on
the falling edge, your processor hold time must not
exceed t
While QSPI can provide the required 20 CLK cycles as
two continuous 10-bit transfers, SPI is limited to 8-bit
transfers. This means that with SPI, a conversion must
consist of three 8-bit transfers. Ensure that the pauses
between 8-bit operations at your selected clock rate
are short enough to maintain a 20ms or shorter conver-
sion time, or the leakage of the capacitive DAC may
cause errors.
B0
SD
CD
is the data setup time for your µP.
S1
CD
f
is the MAX194’s CLK-to-DOUT valid delay
CLK(max)
minimum (100ns).
S0
f
CLK(max)
= /
1
=
2
B13
t
CD
t
CD
+ t
1
+ t
1
SD
SD
t
DH
17