AD7663AST Analog Devices Inc, AD7663AST Datasheet
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AD7663AST
Specifications of AD7663AST
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AD7663AST Summary of contents
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FEATURES Throughput: 250 kSPS INL: 3 LSB Max ( 0.0046% of Full Scale) 16-Bit Resolution with No Missing Codes S/(N+D Typ @ 100 kHz THD: –100 dB Typ @ 100 kHz Analog Input Voltage Ranges Bipolar: 10 ...
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AD7663–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise 2 Bipolar Zero Error , MIN ...
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Parameter 8 TEMPERATURE RANGE Specified Performance NOTES 1 LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the ...
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AD7663 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 17 and 18 (Master Serial Interface Modes) CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert CNVST ...
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... See Analog Inputs section. Specification is for device in free air: 48-Lead LQFP Specification is for device in free air: 48-Lead LFCSP Model Temperature Range AD7663AST –40°C to +85°C AD7663ASTRL –40°C to +85°C AD7663ACP – +85 C AD7663ACPRL – + EVAL-AD7663CB 2 EVAL-CONTROL BRD2 NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes ...
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AD7663 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally Connect. 44–48 4 BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, ...
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Pin No. Mnemonic Type Description 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is ...
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AD7663 DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB ...
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CODE TPC 1. Integral Nonlinearity vs. Code 0.3 0.6 0.9 1.2 1.5 ...
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AD7663 100 95 SNR 90 SINAD FREQUENCY – kHz TPC 7. SNR, S/(N+D), and ENOB vs. Frequency –80 –70 –60 –50 –40 –30 INPUT LEVEL – dB TPC 8. SNR ...
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SAMPLING RATE – SPS TPC 13. Operating Currents vs. Sample Rate 500 450 400 350 300 250 200 150 100 50 0 –55 –35 – ...
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AD7663 4R IND REF 4R REFGND INC 2R INB R INA INGND 111...111 111...110 111...101 000...010 000...001 000...000 –FS – LSB –FS + 0.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function Description 1 Full-Scale Range ±10 ...
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ANALOG SUPPLY (5V ADR421 2.5V REF 1M + NOTE 1 C 50k REF NOTE 2 100nF NOTE 100nF AD8031 NOTE NOTE 5 U1 ANALOG + INPUT 2.7nF ( ...
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AD7663 FREQUENCY – kHz Figure 7. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the AD7663 behaves like a one-pole RC filter consisting of the ...
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Voltage Reference Input The AD7663 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7663 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling between ...
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AD7663 100k 10k 1k 100 100 1k SAMPLING RATE – SPS Figure 10. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion process. The AD7663 is controlled ...
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PARALLEL INTERFACE The AD7663 is configured to use the parallel interface when the SER/PAR is held LOW. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, ...
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AD7663 CS CNVST BUSY t 29 SYNC t 14 SCLK t 15 SDOUT t 16 Figure 17. Master Serial Data Timing for Reading (Read after Convert) CS, RD CNVST BUSY t 17 SYNC ...
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CS BUSY SCLK t 31 SDOUT t 16 SDIN t 33 Figure 19. Slave Serial Data Timing for Reading (Read after Convert) SLAVE SERIAL INTERFACE External Clock The AD7663 is configured to accept an externally supplied serial data clock on ...
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AD7663 CS CNVST BUSY t 3 SCLK SDOUT t 16 Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion Figure 21 shows the detailed timing diagrams of ...
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Because the Serial Port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the Serial Port is properly synchronized to this clock during ...
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AD7663 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown ...
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Revision History Location 4/03—Data Sheet changed from REV REV. B. Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . ...
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