AD7719BR Analog Devices Inc, AD7719BR Datasheet - Page 21

• Manufacturer Part Number: AD7719BR
• Description: IC ADC 16BIT 24BIT DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BR

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On
Reset = 0x00)
The Mode register is an 8-bit register from which data can be
read or to which data can be written. This register configures the
operating modes of the AD7719. Table XII outlines the bit
Bit
Location
MR7
MR6
MR5
MR4
MR3
MR2–MR0 MD2–MD0 Main and Aux ADC Mode Bits.
These bits select the operational mode of the enabled ADC as follows:
MD2
0
0
0
0
1
1
1
1
REV. A
MD1
0
0
1
1
0
0
1
1
M
0
(
R
Bit
Name
0
BUF
0
CHCON
OSCPD
) 0
7
MD0
0
1
0
1
0
1
0
1
B F
B F
B F
B F
B
Description
Power-Down Mode (Power-On Default).
The current sources, power switches, and PLL are shut off in Power-Down mode.
Idle Mode.
In Idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still
provided.
Single Conversion Mode.
In Single Conversion mode, a single conversion is performed on the enabled channels. On completion of the
conversion, the ADC data registers are updated, the relevant flags in the STATUS register are written, and
idle mode is entered with the MD2–MD0 being written accordingly to 001.
Continuous Conversion.
In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate
(see Filter register).
Internal Zero-Scale Calibration.
Internal short automatically connected to the enabled channel(s). Returns to Idle mode (001) when complete.
Internal Full-Scale Calibration.
External V
System Zero-Scale Calibration.
User should connect system zero-scale input to the channel input pins as selected by the CH1/CH0 and
ACH1/ACH0 bits in the control registers.
System Full-Scale Calibration.
User should connect system full-scale input to the channel input pins as selected by the CH1/CH0 and
ACH1/ACH0 bits in the control registers.
U
U
U
U
U
M
F
R
Description
Reserved for Future Use.
Configures the main ADC for buffered or unbuffered mode of operation. If set, the main ADC operates in
unbuffered mode, lowering the power consumption of the AD7719. If cleared, the Main ADC operates
in buffered mode, allowing the user to place source impedances on the front end without contributing gain
errors to the system.
Reserved for Future Use.
Channel Configure Bit.
If this bit is set, the main ADC operates with three pseudodifferential input channels and the aux ADC
does not have AIN3/AIN4 as an input option. If cleared, the main ADC operates with two fully differential
input channels and the aux channel operates as one fully differential input and two single-ended inputs or
as three single-ended inputs.
Oscillator Power-Down Bit.
If this bit is set, placing the AD7719 in standby mode will stop the crystal oscillator, reducing the power
drawn by the AD7719 to a minimum. The oscillator will require 300 ms to begin oscillating when the
ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when the ADC is put
into standby mode and will not require the 300 ms start-up time when the ADC is taken out of standby.
(
6
) 0
REF
is connected automatically to the ADC input for this calibration. Returns to idle mode when complete.
M
0
(
R
Table XII. MODE Register Bit Designations
) 0
5
C
H
C
M
O
R
N
4
(
) 0
–21–
O
designations for the Mode register. MR7 through MR0 indicate
the bit location, with MR denoting the bits are in the Mode register.
MR7 denotes the first bit of the data stream. The number in
parentheses indicates the power-on/reset default status of that bit.
S
C
M
P
R
D
3
(
) 0
M
M
D
R
2
2
(
) 0
M
M
D
R
1
1
(
) 0
M
AD7719
M
D
R
0
0
(
) 0