AD7829BR Analog Devices Inc, AD7829BR Datasheet - Page 16

IC ADC 8BIT 8CH 2MSPS 28-SOIC

AD7829BR

Manufacturer Part Number
AD7829BR
Description
IC ADC 8BIT 8CH 2MSPS 28-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7829BR

Rohs Status
RoHS non-compliant
Number Of Bits
8
Sampling Rate (per Second)
2M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
36mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7829BR
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7829BRU
Manufacturer:
AD
Quantity:
5 510
Part Number:
AD7829BRU
Manufacturer:
PHI
Quantity:
5 510
Part Number:
AD7829BRU-1
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7829BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7829BRUZ-1
Manufacturer:
ADI
Quantity:
1 000
Part Number:
AD7829BRUZ-1
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7829BRUZ-1REEL7
Manufacturer:
ADI
Quantity:
1 000
Part Number:
AD7829BRUZ-1REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD7829BRUZ-REEL7
Quantity:
2 000
Part Number:
AD7829BRWZ-1
Manufacturer:
ADI
Quantity:
1 000
AD7822/AD7825/AD7829
Mode 2 Operation (Automatic Power-Down)
When the AD7822/AD7825/AD7829 are operated in Mode 2
(see Figure 25), they automatically power down at the end of
a conversion. The CONVST signal is brought low to initiate
a conversion and is left logic low until after the EOC goes high,
that is, approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (that is,
530 ns maximum after CONVST falling edge), and the AD7822/
AD7825/AD7829 power down as long as CONVST is low.
DB0 TO DB7
CONVST
DB0 TO DB7
EOC
CONVST
RD
CS
EOC
RD
CS
TRACK
t
t
POWER-UP
2
120ns
HOLD
t
1
t
1
Figure 24. Mode 1 Operation
Figure 25. Mode 2 Operation
Rev. C | Page 16 of 28
The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by powering up the AD7822/AD7825/
AD7829 only to carry out a conversion. The parallel interface of
the AD7822/AD7825/AD7829 remains fully operational while
the ADCs are powered down. A read may occur while the part
is powered down, and, therefore, it does not necessarily need to
be placed within the EOC pulse, as shown in Figure 25.
TRACK
VALID
DATA
VALID
DATA
POWER
DOWN
HERE
t
3
HOLD

Related parts for AD7829BR