AD7685ARM Analog Devices Inc, AD7685ARM Datasheet - Page 18
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AD7685ARM
Manufacturer Part Number
AD7685ARM
Description
IC ADC 16BIT PSEUDO-DIFF 10-MSOP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet
1.AD7685BCPZRL7.pdf
(28 pages)
Specifications of AD7685ARM
Design Resources
Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
Number Of Bits
16
Sampling Rate (per Second)
250k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
15mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-TFSOP (0.118", 3.00mm Width)
For Use With
EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7685ARMZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7685ARMZ-RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7685ARMZRL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7685
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When conversion is completed, the AD7685
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
ACQUISITION
SDI = 1
SDO
CNV
SCK
t
CNVH
CONVERSION
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
t
CONV
t
EN
D15
1
Rev. B | Page 18 of 28
t
HSDO
D14
2
t
CYC
ACQUISITION
D13
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
14
SDI
Figure 34. CS Mode 3-Wire, No BUSY Indicator
AD7685
t
SCK
CNV
SCK
15
Connection Diagram (SDI High)
D1
SDO
16
D0
t
DIS
CONVERT
DATA IN
CLK
DIGITAL HOST