AD7685CCPWP Analog Devices Inc, AD7685CCPWP Datasheet - Page 24
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AD7685CCPWP
Manufacturer Part Number
AD7685CCPWP
Description
IC ADC 16BIT PSEUDO-DIFF 10LFCSP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet
1.AD7685BCPZRL7.pdf
(28 pages)
Specifications of AD7685CCPWP
Design Resources
Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
Number Of Bits
16
Sampling Rate (per Second)
250k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
15mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-WFDFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD7685
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7685
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7685 with all its analog signals on the left side
and all its digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7685 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided
At least one ground plane should be used. It could be common
or split between the digital and analog section. In the latter case,
the planes should be joined underneath the AD7685.
Figure 46. Example of Layout of the AD7685 (Top Layer)
The AD7685 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connected with wide, low impedance traces.
Finally, the power supplies VDD and VIO should be decoupled
with ceramic capacitors, typically 100 nF, placed close to the
AD7685 and connected using short and wide traces to provide
low impedance paths and to reduce the effect of glitches on the
power supply lines.
An example layout following these rules is shown in Figure 46
and Figure 47.
EVALUATING THE PERFORMANCE OF THE AD7685
Other recommended layouts for the AD7690 are outlined in
Figure 47. Example of Layout of the AD7685 (Bottom Layer)
the documentation of the evaluation board (EVAL-AD7685CB).
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the universal evaluation
control board
(EVAL-CONTROL
BRD3).
Rev. B | Page 24 of 28