AD7265BCP Analog Devices Inc, AD7265BCP Datasheet - Page 4

• Manufacturer Part Number: AD7265BCP
• Description: IC ADC 12BIT 3CHAN 1MSPS 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7265BCP

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7265
Parameter
REFERENCE INPUT/OUTPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
1
2
3
4
5
6
7
8
Temperature range is −40°C to +125°C.
See Terminology section.
Sample tested during initial release to ensure compliance.
Guaranteed no missed codes to 12 bits.
V
V
For full common-mode range, see Figure 24 and Figure 25.
Relates to Pin D
IN−
IN−
DC Leakage Current
Input Capacitance
Reference Output Voltage
Long-Term Stability
Output Voltage Hysteresis
Reference Input Voltage Range
DC Leakage Current
Input Capacitance
D
Reference Temperature Coefficient
V
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
Output High Voltage, V
Output Low Voltage, V
Floating State Leakage Current
Floating State Output Capacitance
Output Coding
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
V
V
I
Power Dissipation
DD
REF
DD
DRIVE
CAP
or V
= 0 V for specified performance. For full input range on V
Normal Mode (Static)
Operational, f
Partial Power-Down Mode
Full Power-Down Mode (V
Normal Mode (Operational)
Partial Power-Down (Static)
Full Power-Down (Static)
A, D
Noise
IN+
must remain within GND/V
CAP
B Output Impedance
CAP
A or Pin D
IN
f
S
S
= 1 MSPS
= 1 MSPS
INL
IN
INH
3
CAP
OL
OH
B.
8
2
DD
DD
)
.
3
3
Specification
±1
45
10
2.5
150
50
0.1/V
±2
25
10
20
10
20
2.8
0.4
±15
5
V
0.4
±1
7
14
90
110
1
2.7/5.25
2.7/5.25
2.3
4
3.2
500
1
2.8
21
2.625
5.25
DRIVE
IN−
pin, see Figure 28 and Figure 29.
DD
− 0.2
Straight (natural) binary
Twos complement
Rev. A | Page 4 of 28
SCLK cycles
ns max
ns max
MSPS max
V min/V max
V min/V max
mA max
mA max
mA max
μA max
μA max
μA max
mW max
mW max
μW max
Unit
μA max
pF typ
pF typ
V min/V max
ppm typ
ppm typ
V min/V max
μA max
pF typ
Ω typ
ppm/°C max
ppm/°C typ
μV rms typ
V min
V max
nA typ
pF typ
V min
V max
μA max
pF typ
Test Conditions/Comments
When in track
When in hold
±0.2% max @ 25°C
For 1000 hours
See Typical Performance Characteristics section
External reference applied to Pin D
V
SGL/DIFF = 1 with 0 V to V
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V
875 ns with SCLK = 16 MHz
Full-scale step input; V
Full-scale step input; V
Digital I/Ps = 0 V or V
V
V
V
Static
T
T
V
V
V
A
A
IN
DD
DD
DD
DD
DD
DD
= −40°C to +85°C
> 85°C to 125°C
= 0 V or V
= 5.25 V
= 5.25 V; 3.5 mA typ
= 3.6 V; 2.7 mA typ
= 5.25 V
= 5.25 V
= 5.25 V, T
DRIVE
A
= −40°C to +85°C
DRIVE
DD
DD
= 5 V
= 3 V
REF
range selected
CAP
A/Pin D
REF
range
CAP
B