AD7623AST Analog Devices Inc, AD7623AST Datasheet - Page 8

• Manufacturer Part Number: AD7623AST
• Description: IC ADC 16BIT 1.33MSPS DFF 48LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7623AST

• Number Of Bits: 16
• Sampling Rate (per Second): 1.33M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 55mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: EVAL-AD7623CBZ - BOARD EVALUATION FOR AD7623
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7623
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 41, 42
2, 44
3, 40
4
5
6, 7
8
9, 10
11, 12
13
14
15
Mnemonic
AGND
AVDD
NC
BYTESWAP
OB/2C
DGND
SER/PAR
D[0:1]
D[2:3]
or
DIVSCLK[0:1]
D4
or EXT/INT
D5
or INVSYNC
D6
or INVSCLK
Type
P
P
DI
DI
P
DI
DO
DI/O
DI/O
DI/O
DI/O
1
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 2.5 V.
No Connect.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
Digital Power Ground.
Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus
are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low,
the parallel port is selected.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus.
When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR = high, serial clock division selection. When using serial master read after convert
mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally
generated serial clock that clocks the data output. In other serial modes, these pins are high
impedance outputs.
When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR = high, serial clock source select. This input is used to select the internally generated
(master ) or external (slave) serial data clock.
When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated
by CS, connected to the SCLK input.
When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
When SER/ PAR = low, this output is used as Bit 6 of the parallel port data output bus.
Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
NC = NO CONNECT
D2/DIVSCLK[0]
D3/DIVSCLK[1]
BYTESWAP
SER/PAR
OB/2C
AGND
DGND
DGND
AVDD
NC
D0
D1
10
11
12
1
2
3
4
5
6
7
8
9
Figure 4. Pin Configuration
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44
PIN 1
IDENTIFIER
Rev. 0 | Page 8 of 28
(Not to Scale)
TOP VIEW
AD7623
43 42 41 40
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12