AD7745ARUZ Analog Devices Inc, AD7745ARUZ Datasheet - Page 5

• Manufacturer Part Number: AD7745ARUZ
• Description: IC CONV 1CH CAP TO DGTL 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Capacitance-to-Digital Converterr

Specifications of AD7745ARUZ

• Design Resources: Extending the Capacitive Input Range of AD7745/AD7746 (CN0129)
• Resolution (bits): 24 b
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Supply Current: 750µA
• Power Dissipation Pd: 4.25mW
• Inl ±: 100ppm
• Sample Rate: 90SPS
• Supply Voltage Max: 5.25V
• Input Channels Per Adc: 1
• No. Of Bits: 24 Bit
• Features: 24Bit Capacitance To Digital Convert I.C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
V
Table 2.
Parameter
SERIAL INTERFACE
1
2
Sample tested during initial release to ensure compliance.
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
DD
SCL Frequency
SCL High Pulse Width, t
SCL Low Pulse Width, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Hold Time (Start Condition), t
Set-Up Time (Start Condition), t
Data Set-Up Time, t
Data Set-Up Time, t
Set-Up Time (Stop Condition), t
Data Hold Time, t
Bus-Free Time (Between Stop and Start Condition, t
= 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V
SDA
SCL
1, 2
P
HD;DAT
t
BUF
SU;DAT
SU;DAT
F
R
S
LOW
(Master)
HIGH
t
HD:STA
HD;STA
t
SU;STO
SU;STA
LOW
t
R
t
HD:DAT
Figure 3. Serial Interface Timing Diagram
BUF
t
HIGH
)
t
F
t
SU:DAT
Min
0
0.6
1.3
0.6
0.6
0.25
0.35
0.6
0
1.3
Rev. 0| Page 5 of 28
Typ
400
0.3
0.3
Max
S
t
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
SU:STA
t
HD:STA
DD
; –40°C to +125°C, unless otherwise noted.
Test Conditions/Comments
See Figure 3
After this period, the first clock is generated
Relevant for repeated start condition
V
V
DD
DD
≥ 3.0 V
< 3.0 V
t
SU:STO
AD7745/AD7746
P