AD7873ARU-REEL7 Analog Devices Inc, AD7873ARU-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD7873ARU-REEL7
• Description: IC ADC 12BIT TOUCHSCREEN 16TSSOP
• Manufacturer: Analog Devices Inc
• Type: Resistiver

Specifications of AD7873ARU-REEL7

• Rohs Status: RoHS non-compliant
• Touch Panel Interface: 4-Wire
• Number Of Inputs/keys: 1 TSC
• Resolution (bits): 12 b
• Data Interface: Serial
• Data Rate/sampling Rate (sps, Bps): 125k
• Voltage Reference: External, Internal
• Voltage - Supply: 2.2 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Voltage Supply Source: Single Supply
• Sampling Rate (per Second): 125k
• Lead Free Status / RoHS Status: Not Compliant

TIMING SPECIFICATIONS
T
Table 2. Timing Specifications
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
DCLK
ACQ
1
2
3
4
5
6
7
8
9
10
11
12
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the DCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
A
3
3
12
4
= T
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
2
MIN
to T
MAX
, unless otherwise noted; V
Limit at T
10
2
1.5
10
60
60
200
200
60
10
10
200
0
100
100
MIN
1
, T
MAX
Figure 2. Load Circuit for Digital Output Timing Specifications
Unit
kHz min
MHz max
μs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
CC
= 2.7 V to 5.25 V, V
TO OUTPUT
PIN
50pF
Description
Acquisition time
CS falling edge to first DCLK rising edge
CS falling edge to busy three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
Rev. E | Page 5 of 28
C
L
200µA
200µA
REF
= 2.5 V.
I
I
OL
OH
1.6V
12
, quoted in the timing characteristics is the true bus relinquish
CC
) and timed from a voltage level of 1.6 V.
AD7873