TDA8754HL/14/C1,55 NXP Semiconductors, TDA8754HL/14/C1,55 Datasheet - Page 17
![IC TRPL 8BIT VIDEO ADC 144LQFP](/photos/6/65/66527/tda8754hl14be-s_sml.jpg)
TDA8754HL/14/C1,55
Manufacturer Part Number
TDA8754HL/14/C1,55
Description
IC TRPL 8BIT VIDEO ADC 144LQFP
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet
1.TDA8754HL14C155.pdf
(57 pages)
Specifications of TDA8754HL/14/C1,55
Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
270M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Operating Supply Voltage
3 V to 3.6 V
Supply Current
180 mA
Maximum Operating Temperature
+ 70 C
Maximum Power Dissipation
1.3 W
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2057
935272706551
TDA8754HL14BE-S
935272706551
TDA8754HL14BE-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TDA8754HL/14/C1,55
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 14984
Product data sheet
8.6 Programmable coast
8.7 Data enable
8.8 Sync separator
The maximum hum perturbation is 250 mV (p-p) at 60 Hz to have a correct SOG
functionality.
Table 5:
[1]
When the values of PRECOAST[2:0] = 0 and POSTCOAST[4:0] = 0, the coast pulse
equals the Vsync input.
When an interlaced signal is used, the regenerated coast pulse width may vary from one
frame to another of one Hsync pulse. In that case, the programmed value of
PRECOAST[2:0] needs to be increased by one compared to the expected minimum
number of Hsync coast pulses before the vertical sync signal.
This signal qualifies the active data period on the horizontal line. Pin DEO = HIGH during
the active display time and LOW during the blank time. The start of this signal can be
adjusted with bits HSYNCL[9:0] and HBACKL[9:0]. The length of this signal can be
adjusted with bits HDISPL[11:0].
The sync separator is compatible with TV, HDTV and VESA standards.
If the green video signal has composite sync on it (sync-on-green), the SOG function
allows to separate the Chsync and the active video part. The Chsync signal coming from
this SOG function is accessible through pin CSYNCO.
It is possible to extract the Hsync and the Vsync signals by using the sync separator from
this (C)Hsync signal coming from SOG or coming from the (C)Hsync input.
This function is able to get rid of the additional synchronization pulses in vertical blanking
like equalization or serration pulses.
BITS SOGI[1:0]
00
01
10
11
Definitions:
— Tvideo = total time in 2 frames when video signal is strictly superior to black level.
— Tline = total time of 2 frames.
— Tsync = total time in 2 frames when the video signal is strictly inferior to black level.
Charge pump current programming; see note
Maximum value
83.5 %
86.0 %
90.5 %
test mode
Tvideo/ Tline
Rev. 06 — 16 June 2005
14.8 %
12.6 %
8.6 %
Tsync/ Tline
Triple 8-bit video ADC up to 270 Msps
1
Standard
TV standards and non-VESA
standards
all TV, HDTV and VESA standards
HDTV standards or non-VESA
standards
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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