TDA8754HL/17/C1,51 NXP Semiconductors, TDA8754HL/17/C1,51 Datasheet - Page 18
![IC TRPL 8BIT VIDEO ADC LQFP144](/photos/6/65/66532/144-lqfp_sot486-1_pkg_sml.jpg)
TDA8754HL/17/C1,51
Manufacturer Part Number
TDA8754HL/17/C1,51
Description
IC TRPL 8BIT VIDEO ADC LQFP144
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet
1.TDA8754HL14C155.pdf
(57 pages)
Specifications of TDA8754HL/17/C1,51
Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
170M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935272703518
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
TDA8754HL17BE-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TDA8754HL/17/C1,51
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9. I
9397 750 14984
Product data sheet
2
C-bus register description
9.1.1 Write 1 register
8.9 3-level
9.1 I
When the synchronization pulse of the input of the SOG is 3-level, the system will be able
to detect that a 3-level sync is present and will advise the customer if a change is
observed by setting bit HPDO = 1 and pin HPDO = HIGH. It is possible to disable this
function with bit FTRILEVEL. When this automatic function is disabled, the manual mode
will only influence the separator circuitry.
Each register is programmed independently by giving its subaddress and its data content.
Table 6:
Table 7:
SDA line Description
S
Byte 1
A
Byte 2
A
Byte 3
A
P
2
C-bus formats
Byte 1
Byte 2
Byte 3
Bits
master starts with a start condition
master transmits device address (7 bits) plus write command bit (R/W = 0)
slave generates an acknowledge
master transmits programming mode and register subaddress to write to
slave generates an acknowledge
master transmits data 1
slave generates an acknowledge
master generates a stop condition
I
Byte format for writing 1 register
2
C-bus sequence for writing 1 register
D7
A6
7
1
X
-
programming mode
Rev. 06 — 16 June 2005
D6
A5
X
6
0
-
MODE
A4
D5
5
0
0
device address
SA4
A3
D4
4
1
-
data 1
Triple 8-bit video ADC up to 270 Msps
SA3
A2
D3
3
1
-
register subaddress
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SA2
A1
D2
2
0
-
TDA8754
SA1
D1
A0
X
1
-
R/W
SA0
18 of 57
D0
0
0
-
-