AD5161BRMZ100 Analog Devices Inc, AD5161BRMZ100 Datasheet - Page 16

• Manufacturer Part Number: AD5161BRMZ100
• Description: IC DGTL POT SPI 100K 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5161BRMZ100

• Temperature Coefficient: 45 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Memory Type: Volatile
• Interface: I²C, SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• No. Of Steps: 256
• Resistance Tolerance: ± 30%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, I2C
• No. Of Pots: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5161
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V
voltage applied to terminals A and B is
For a more accurate calculation, which includes the effect of
wiper resistance, V
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I
is engaged.
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 contains a 3-wire SPI compatible digital interface
(SDI, CS , and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Figure 37
V
V
W
W
(
(
D
D
)
)
=
=
).
256
R
D
WB
256
W
W
V
, can be found as
(
with respect to ground for any valid input
A
D
)
+
V
256
A
256
+
−
R
D
DD
WA
256
V
WA
to GND, which must be
B
(
D
and R
)
V
Table 6
B
WB
and not the
.
2
C mode
Rev. A | Page 16 of 20
(3)
(4)
Daisy-Chain Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the V
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 43). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 6, go to U2 and the second eight bits with the
same format go to U1. CS should be kept low until all 16 bits are
clocked into their respective serial registers. After this, CS is
pulled high to complete the operation and load the RDAC latch.
If the data word during the CS low period is greater than 16
bits, any additional MSBs will be discarded.
I
The AD5161 can also be controlled via an I
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The first byte of the AD5161 is a slave address byte (see Table 7
and Table 8). It has a 7-bit slave address and a R/ W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I
on one bus.
The 2-wire I
1.
2
C Compatible 2-Wire Serial Bus (DIS = 1)
CLK
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 40). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/ W bit (this bit
determines whether data will be read from or written to
the slave device).
μC
MOSI
SC
DD
2
C serial bus protocol operates as follows:
supply voltage. It is recommended to increase the
Figure 43. Daisy-Chain Configuration
SDI
CS
AD5161
U1
CLK
SDO
V
DD
R
2.2kΩ
P
2
C compatible devices
2
C compatible serial
SDI
AD5161
CS
U2
CLK
SDO