AD5242BRZ1M Analog Devices Inc, AD5242BRZ1M Datasheet - Page 15

• Manufacturer Part Number: AD5242BRZ1M
• Description: IC POT DGTL DUAL 256POS 16SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5242BRZ1M

• Taps: 256
• Resistance (ohms): 1M
• Number Of Circuits: 2
• Temperature Coefficient: 30 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Resistance In Ohms: 1.00M
• End To End Resistance: 1Mohm
• Track Taper: Linear
• No. Of Steps: 256
• Resistance Tolerance: +50, -30%
• Supply Voltage Range: 2.7V To 5.5V, ± 2.3V To ± 2.7V
• Control Interface: I2C, Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5242EBZ - BOARD EVALUATION FOR AD5242
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5241/AD5242 feature additional programmable logic
outputs, O
switches, and logic gates. They can also be used as a self-contained
shutdown preset to Logic 0 that is further explained in the
Shutdown Function section. O
power-up. The logic states of O
Frame 2 under the write mode (see Figure 4). Figure 34 shows
the output stage of O
channel MOSFETs in push-pull configuration. As shown in
Figure 34, the output is equal to V
outputs have adequate current driving capability to drive
milliamperes of load.
Users can also activate O
ways without affecting the wiper settings:
1.
2.
3.
All digital inputs are protected with a series input resistor and
the parallel Zener ESD structures shown in Figure 36. This
applies to the digital input pins, SDA, SCL, and SHDN .
Start, slave address byte, acknowledge, instruction byte
with O
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O
acknowledge, stop.
Do not complete the write cycle by not issuing the stop,
then start, slave address byte, acknowledge, instruction
byte with O
1
1
and O
and O
Figure 34. Output Stage of Logic Output, O
IN
O
OF WRITE MODE
1
1
DATA IN FRAME 2
and O
2
, that can be used to drive digital load, analog
2
specified, acknowledge, stop.
1
, which employs large P-channel and N-
1
1
2
and O
specified, acknowledge, stop.
1
2
2
1
and O
in the following three different
and O
DD
M
M
P
N
or V
2
2
default to Logic 0 during
V
V
can be programmed in
DD
SS
SS
, and these logic
O
1
1
and O
1
2
specified,
Rev. C | Page 15 of 20
SHUTDOWN FUNCTION
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte (see
Table 2
only) is placed in shutdown mode by the software, SD bit, the
part returns the wiper to its prior position when a new command
is received.
In addition, shutdown can be implemented with the device digital
output, as shown in Figure 35. In this configuration, the device
is shutdown during power-up but users are allowed to program
the device. Thus, when O
shutdown mode and responds to the new setting. This self-contained
shutdown function allows absolute shutdown during power-up,
which is crucial in hazardous environments, and it does not add
extra components.
). If the RDAC Register 1 or RDAC Register 2 (AD5242
Figure 35. Shutdown by Internal Logic Output, O
Figure 37. ESD Protection of Resistor Terminals
Figure 36. ESD Protection of Digital Pins
R
340
PD
A,B,W
1
Ω
is programmed high, the device exits
V
V
SS
O
SHDN
SDA
SCL
SS
1
LOGIC
AD5241/AD5242
1