MAX5392MAUE+ Maxim Integrated Products, MAX5392MAUE+ Datasheet - Page 11

• Manufacturer Part Number: MAX5392MAUE+
• Description: IC POT DGTL 256-TAP 16TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5392MAUE+

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 200 Ohms
• Wiper Memory: Volatile
• Digital Interface: I2C
• Operating Supply Voltage: 1.7 V to 5.5 V
• Supply Current: 27 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Dual Volatile Low Voltage Linear Taper Digital Potentiometer
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each transmission consists of a START (S) condition sent
by a master, followed by a 7-bit slave address plus a
NOP/W bit. See Figures 3, 4, and 7.
SCL and SDA remain high when the interface is inactive.
A master controller signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master controller
issues a STOP condition by transitioning the SDA from
low to high while SCL is high, after finishing communi-
cating with the slave. The bus is then free for another
transmission. See Figure 2.
Figure 3. START and STOP Conditions
Figure 4. Slave Address
Figure 5. Bit Transfer
SDA
START
SCL
SDA
SCL
SDA
SCL
START CONDITION
______________________________________________________________________________________
S
0
MSB
START and STOP Conditions
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
1
DATA STABLE,
DATA VALID
0
1
DATA ALLOWED
CHANGE OF
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable while SCL is
high. See Figure 5.
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data. See
Figure 6. Each byte transferred requires a total of 9 bits.
The master controller generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line remains stable low during
the high period of the clock pulse.
A2
A1
LSB
A0
NOP/W
CONDITION
STOP
P
ACK
Acknowledge
Bit Transfer
11