DS3930E+ Maxim Integrated Products, DS3930E+ Datasheet - Page 4

• Manufacturer Part Number: DS3930E+
• Description: IC POT NV HEX I/O MEM 20-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS3930E+

• Taps: 256
• Resistance (ohms): 16.5K
• Number Of Circuits: 6
• Temperature Coefficient: 250 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 16.5K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hex Nonvolatile Potentiometer with
I/O and Memory
AC ELECTRICAL CHARACTERISTICS (continued)
(V
EEPROM CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
4
Data Hold Time (Notes 3, 5, 7)
Data Setup Time (Note 3)
Start Setup Time (Note 3)
Rise Time of Both SDA and SCL
Signals (Note 7)
Fall Time of Both SDA and SCL
Signals (Note 7)
Setup Time for STOP Condition
Capacitive Load for Each Bus
EEPROM Write Time
Writes
CC
CC
______________________________________________________________________
= +2.7V to +5.5V; T
= +2.7V to +5.5V; T
PARAMETER
PARAMETER
All voltages are referenced to ground.
I
A fast-mode device can be used in a standard-mode system, but the requirement t
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
The maximum t
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
nal) in order to bridge the undefined region of the falling edge of SCL.
C
EEPROM write begins after a STOP condition occurs.
STBY
B
—total capacitance of one bus line in picofarads, timing referenced to 0.9V
specified for V
A
A
HD:DAT
= -40°C to +85°C, unless otherwise specified.)
= -40°C to +85°C, unless otherwise specified.)
CC
has only to be met if the device does not stretch the LOW period (t
equal 3.0V and 5.0V, SDA = SCL = V
SYMBOL
SYMBOL
t
t
t
t
HD:DAT
SU:DAT
SU:STA
SU:STO
C
t
t
t
W
R
F
B
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 7)
(Note 8)
+70°C
CONDITIONS
CONDITIONS
CC
, and I/O
0
= I/O
CC
1
= I/O
and 0.1V
SU:DAT
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
50,000
2
MIN
MIN
100
250
0.6
4.7
0.6
4.0
0
0
= I/O
RMAX
LOW
> 250ns must then be met.
CC.
3
) of the SCL signal.
= A0 = A1 = A2 = GND.
B
B
B
B
TYP
+ t
TYP
5
IH MIN
SU:DAT
of the SCL sig-
MAX
1000
MAX
300
300
300
400
0.9
0.9
= 1000ns
20
UNITS
UNITS
ms
pF
µs
ns
µs
ns
ns
µs