DS1846E-010+ Maxim Integrated Products, DS1846E-010+ Datasheet - Page 18

• Manufacturer Part Number: DS1846E-010+
• Description: IC NV TRI-POT MEM MON 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1846E-010+

• Taps: 100, 256
• Resistance (ohms): 10K, 100K
• Number Of Circuits: 3
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 10K, 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTES:
1) All voltages are referenced to ground.
2) I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
3) I
4) A fast-mode device can be used in a standard mode system, but the requirement t
5) After this period, the first clock pulse is generated.
6) The maximum t
7) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
8) C
9) EEPROM write begins after a stop condition occurs.
10) Resistor inputs can not go beneath GND by more than 0.5V or above V
11) Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
12) Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
13) When used as a rheostat or variable resistor the temperature coefficient applies: 750ppm/°C. When
14) Valid for V
15) Valid at +25°C only.
16) Noise immunity pulses < 2ms at V
Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
corresponding inactive state. All inputs should be connected high.
then be met. This is automatically the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit
to the SDA line t
SCL signal.
MIN
positions.
used as a voltage-divider or potentiometer, the effective temperature coefficient approaches
30ppm/°C.
STBY
B
—total capacitance of one bus line in picofarads, timing referenced to (0.9 x V
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
specified with V
CC
= 5V only.
HD:DAT
RMAX
CC
+ t
has only to be met if the device does not stretch the low period (t
= 5.0V and control port logic pins are driven to the appropriate logic levels.
SU:DAT
= 1000ns + 250ns = 1250ns before the SCL line is released.
CCTP
minimum do not cause a reset.
18 of 18
CC
by more than 0.5V.
CC
is switched off.
SU:DAT
CC
CC
) and (0.1 x V
for the
> 250ns must
LOW
) of the
CC
IN
).