MCP4141-503E/SN Microchip Technology, MCP4141-503E/SN Datasheet - Page 36
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MCP4141-503E/SN
Manufacturer Part Number
MCP4141-503E/SN
Description
IC POT DGTL SNGL 50K SPI 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.MCP4161-502ESN.pdf
(88 pages)
Specifications of MCP4141-503E/SN
Memory Type
Non-Volatile
Taps
129
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
50K
End To End Resistance
50kohm
Resistance Tolerance
± 20%
No. Of Steps
129
Supply Voltage Range
2.7V To 5.5V
Control Interface
SPI
No. Of Pots
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MCP414X/416X/424X/426X
5.2
Each tap point (between the R
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero-scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full-scale connections, connects the Terminal
W (wiper) to Terminal A (wiper setting of 100h or 80h).
In these configurations the only resistance between the
Terminal W and the other Terminal (A or B) is that of the
analog switches.
A wiper setting value greater than full scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a Full Scale setting (Terminal W (wiper)
connected to Terminal A).
wiper setting map.
Equation 5-2
mine the resistance between the wiper and terminal B.
EQUATION 5-2:
TABLE 5-1:
DS22059B-page 36
7-bit Pot 8-bit Pot
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
Wiper Setting
N = 0 to 256 (decimal)
N = 0 to 128 (decimal)
R
R
Wiper
WB
WB
=
=
illustrates the calculation used to deter-
3FFh
0FFh
101h
100h
080h
07Fh
000h
081
001
R
------------- -
(
R
------------- -
(
256
128
AB
AB
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
N
N
)
)
+
+
R
Reserved (Full Scale (W = A)),
Increment and Decrement
commands ignored
Full Scale (W = A),
Increment commands ignored
W = N
W = N (Mid-Scale)
W = N
Zero Scale (W = B)
Decrement command ignored
WB
R
R
W
W
Table 5-1
CALCULATION
Properties
8-bit Device
7-bit Device
S
illustrates the full
resistors) is a
5.3
The MCP4XXX device’s WiperLock technology allows
application-specific calibration settings to be secured in
the EEPROM without requiring the use of an additional
write-protect pin. There are two WiperLock Technology
configuration bits (WL0 and WL1). These bits prevent
the Non-Volatile and Volatile addresses and bits for the
specified resistor network from being written.
The WiperLock technology prevents the serial
commands from doing the following:
• Changing a volatile wiper value
• Writing to a non-volatile wiper memory location
• Changing the volatile TCON register value
For either Resistor Network 0 or Resistor Network 1
(Potx), the WLx bit controls the following:
• Non-Volatile Wiper Register
• Volatile Wiper Register
• Volatile TCON register bits RxHW, RxA, RxW, and
High Voltage commands are required to enable and
disable WiperLock. Please refer to the
Protect or WiperLock Technology (High Voltage)
command for operation.
5.3.1
The WiperLock Technology state is not affected by a
POR/BOR event. A POR/BOR event will load the
Volatile Wiper register value with the Non-Volatile
Wiper register value, refer to Section 4.1.
RxB
WiperLock™ Technology
POR/BOR OPERATION WHEN
WIPERLOCK TECHNOLOGY
ENABLED
© 2008 Microchip Technology Inc.
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