MCP4241-503E/SL Microchip Technology, MCP4241-503E/SL Datasheet - Page 51
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MCP4241-503E/SL
Manufacturer Part Number
MCP4241-503E/SL
Description
IC DGTL POT 50K 2CH 14SOIC
Manufacturer
Microchip Technology
Datasheet
1.MCP4161-502ESN.pdf
(88 pages)
Specifications of MCP4241-503E/SL
Memory Type
Non-Volatile
Taps
129
Resistance (ohms)
50K
Number Of Circuits
2
Temperature Coefficient
150 ppm/°C Typical
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Resistance In Ohms
50K
End To End Resistance
50kohm
Resistance Tolerance
± 20%
No. Of Steps
129
Supply Voltage Range
2.7V To 5.5V
Control Interface
SPI
No. Of Pots
Dual
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4241-503E/SL
Manufacturer:
Microchip
Quantity:
724
7.6
The Read command is a 16-bit command. The Read
Command can be issued to both the Volatile and
Non-Volatile memory locations. The format of the
command is shown in
The first 6-bits of the Read command determine the
address and the command. The 7th clock will output
the CMDERR bit on the SDO pin. The remaining
9-clocks the device will transmit the 9 data bits (D8:D0)
of the specified address (AD3:AD0).
Figure 7-4
Read command.
During a write cycle (Write or High Voltage Write to a
Non-Volatile memory location) the Read command can
only read the Volatile memory locations. By reading the
Status Register (04h), the Host Controller can
determine when the write cycle has completed (via the
state of the EEWA bit).
FIGURE 7-4:
© 2008 Microchip Technology Inc.
SDI
SDO
A
D
3
1
1
Read Data
Normal and High Voltage
shows the SDI and SDO information for a
D
A
2
1
1
COMMAND BYTE
D
A
1
1
1
D
A
0
1
1
Figure
Read Command - SDI and SDO States.
1
1
1
1
1
1
7-4.
X
1
0
D
X
8
0
D
X
7
0
D
X
6
0
READ DATA
X
D
5
0
MCP414X/416X/424X/426X
DATA BYTE
X
D
4
0
X
D
3
0
X
D
2
0
7.6.1
The read operation requires that the CS pin be in the
active state (V
the inactive state (V
(V
Byte and Data Byte) is then clocked in on the SCK and
SDI pins. The SDO pin starts driving data on the 7th bit
(CMDERR bit) and the addressed data comes out on
the 8th through 16th clocks.
Figure 6-6
Figure 6-5
waveforms when the SDI and SDO signals are
multiplexed on the same pin. For additional information
on the multiplexing of these signals, refer to
Section 6.1.3 “SDI/SDO”.
D
X
1
0
IL
or V
D
X
0
0 Attempted Non-Volatile Memory Read
IHH
Valid Address/Command combination
during Non-Volatile Memory Write Cycle
show possible waveforms for a single read.
). The 16-bit Read Command (Command
SINGLE READ
and
IL
or V
Figure 6-6
IHH
IH
) and is driven to the active state
). Typically, the CS pin will be in
show the single read
Figure 6-3
DS22059B-page 51
through