MAX5388NAUB+ Maxim Integrated Products, MAX5388NAUB+ Datasheet - Page 8

• Manufacturer Part Number: MAX5388NAUB+
• Description: IC POT DGTL 256-TAP 10UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX5388NAUB+

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 200 Ohms
• Wiper Memory: Volatile
• Digital Interface: Serial (3-Wire, SPI)
• Operating Supply Voltage: 2.6 V to 5.5 V
• Supply Current: 1 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Dual Volatile Low Voltage Linear Taper Digital Potentiometer
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.6 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
The MAX5386/MAX5388 dual, 256-tap, volatile low-volt-
age linear taper digital potentiometers offer three end-to-
end resistance values of 10kI, 50kI, and 100kI. Each
potentiometer consists of 255 fixed resistors in series
between terminals H and L. The potentiometer wiper, W,
is programmable to access anyone of the 256 tap points
on the resistor string.
The potentiometers in each device are programmable
independently of each other. The MAX5386/MAX5388
have an SPI interface.
The MAX5386/MAX5388 include an SPI interface, which
provides a 3-wire write-only serial data interface to con-
trol the wiper tap position through inputs chip select
(CS), data in (DIN), and data clock (SCLK). Drive CS
low to load data from DIN synchronously into the serial
shift register on the rising edge of each SCLK pulse.
The MAX5386/MAX5388 load the last 9 bits of clocked
data once CS transitions high. See Figures 2 and 3.
After all the data bits are shifted in, data are latched into
the appropriate potentiometer control register when CS
goes from low to high. Data written to a memory register
immediately updates the wiper position. Keep CS low
Table 1. SPI Register Map
8
Bit Number
Bit Name
Write Wiper Register A
Write Wiper Register B
______________________________________________________________________________________
Detailed Description
SPI Digital Interface
A0
1
0
1
D7
D7
D7
2
D6
D6
D6
3
during the entire data stream to prevent the data from
being terminated.
The first bit A0 (address bit) addresses one of the two
potentiometers; writing a zero in A0 addresses control
register A and writing a one in A0 addresses control reg-
ister B. See Table 1. The power-on reset (POR) circuitry
sets the wiper to midscale (D[7:0] 1000 0000).
The 8 data bits (D7–D0) indicate the position of the
wiper. For D[7:0] = 0000 0000, the wiper moves to the
position closest to L. For D[7:0] = 1111 1111, the wiper
moves closest to H. D[7:0] is 1000 0000 following power-
on for both registers A and B.
Register A: The data byte writes to register A, and the
wiper of potentiometer A moves to the appropriate posi-
tion at the rising edge of CS. D[7:0] indicates the posi-
tion of the wiper. D[7:0] = 0000 0000 moves the wiper to
the position closest to L. D[7:0] = 1111 1111 moves the
wiper to the position closest to H. D[7:0] is 1000 0000
following power-on.
Register B: The data byte writes to register B, and the
wiper of potentiometer B moves to the appropriate posi-
tion at the rising edge of CS. D[7:0] indicates the posi-
tion of the wiper. D[7:0] = 0000 0000 moves the wiper to
the position closest to L. D[7:0] = 1111 1111 moves the
wiper to the position closest to H. D[7:0] is 1000 0000
following power-on.
D5
D5
D5
4
D4
D4
D4
5
D3
D3
D3
6
D2
D2
D2
7
D1
D1
D1
8
D0
D0
D0
9