MAX5387LAUD+ Maxim Integrated Products, MAX5387LAUD+ Datasheet - Page 10

• Manufacturer Part Number: MAX5387LAUD+
• Description: IC POT DGTL 256-TAP 14TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5387LAUD+

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 10K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 200 Ohms
• Wiper Memory: Volatile
• Digital Interface: I2C
• Operating Supply Voltage: 2.6 V to 5.5 V
• Supply Current: 1 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Dual Low Voltage Digital Potentiometer
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.6 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Acknowledge
Dual, 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable while SCL is
high. See Figure 4.
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data. See
Figure 5. Each byte transferred requires a total of nine
bits. The master controller generates the 9th clock pulse,
and the recipient pulls down SDA during the acknowl-
edge clock pulse, so the SDA line remains stable low
during the high period of the clock pulse.
Figure 3. START and STOP Conditions
Figure 4. Bit Transfer
10
_____________________________________________________________________________________
SCL
SDA
CONDITION
START
SDA
SCL
SDA
SCL
START CONDITION
S
1
DATA STABLE,
DATA VALID
Acknowledge
Bit Transfer
2
DATA ALLOWED
CHANGE OF
The MAX5387 includes a 7-bit slave address (Figure 6).
The 8th bit following the 7th bit of the slave address is the
NOP/W bit. Set the NOP/W bit low for a write command
and high for a no-operation command. The device does
not support readback.
The device provides three address inputs (A0, A1, and
A2), allowing up to eight devices to share a common
bus (Table 1). The first 4 bits (MSBs) of the factory-set
slave addresses are always 0101. A2, A1, and A0 set the
next 3 bits of the slave address. Connect each address
input to V
address to share a common bus.
DD
or GND. Each device must have a unique
8
NOT ACKNOWLEDGE
ACKNOWLEDGMENT
CLOCK PULSE FOR
ACKNOWLEDGE
9
CONDITION
STOP
Slave Address
P