MCP42010T-I/ST Microchip Technology, MCP42010T-I/ST Datasheet - Page 21
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MCP42010T-I/ST
Manufacturer Part Number
MCP42010T-I/ST
Description
IC POT DGTL 10K 2CH SPI 14-TSSOP
Manufacturer
Microchip Technology
Datasheet
1.MCP41010-ISN.pdf
(32 pages)
Specifications of MCP42010T-I/ST
Package / Case
14-TSSOP
Taps
256
Resistance (ohms)
10K
Number Of Circuits
2
Temperature Coefficient
800 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Resistance In Ohms
10K
Number Of Pots
Dual
Taps Per Pot
256
Resistance
10 KOhms
Buffered Wiper
Buffered
Digital Interface
Serial
Operating Supply Voltage
2.7 V to 5.5 V
Supply Current
340 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Description/function
256 Step SPI 10k Ohm with SPI Interface
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP4XXXDM-DB - BOARD DAUGHTER DIGIPOT MCP4XXX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP42010T-I/ST
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP42010T-I/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.5
The Reset pin (RS) will automatically set all potentiom-
eter data latches to mid-scale (Code 80h) when pulled
low (provided that the pin is held low at least 150 ns
and CS is high). The reset will execute regardless of
the position of the SCK, SHDN and SI pins. It is possi-
ble to toggle RS low and back high while SHDN is low.
In this case, the potentiometer registers will reset to
mid-scale, but the potentiometer will remain in
shutdown mode until the SHDN pin is raised.
5.6
When held low, the shutdown pin causes the applica-
tion circuit to go into a power-saving mode by open-cir-
cuiting the A terminal and shorting the B and W
terminals for all potentiometers. Data register contents
are not affected by entering shutdown mode (i.e., when
the SHDN pin is raised, the data register contents are
the same as before the shutdown mode was entered).
While in shutdown mode, it is still possible to clock in
new values for the data registers, as well as toggling
the RS pin to cause all data registers to go to mid-scale.
The new values will take affect when the SHDN pin is
raised.
If the device is powered-up with the SHDN pin held low,
it will power-up in the shutdown mode with the data reg-
isters set to mid-scale.
5.7
When the device is powered on, the data registers will
be set to mid-scale (80h). A power-on reset circuit is
utilized to ensure that the device powers up in this
known state.
2003 Microchip Technology Inc.
Note:
Note:
Reset (RS) Pin Operation
Shutdown (SHDN) Pin Operation
Power-up Considerations
Bringing the RS pin low while the CS pin is
low constitutes an invalid operating state
and will result in indeterminate results
when RS and/or CS are brought high.
Bringing the SHDN pin low while the CS
pin is low constitutes an invalid operating
state and will result in indeterminate
results when SHDN and/or CS are brought
high.
TABLE 5-1:
SCK
Ø
X
X
X
X
X
X
X
L
¦
MCP41XXX/42XXX
CS
Ø
H
H
H
H
H
L
L
L
¦
RS
H
H
H
H
H
H
Ø
Ø
H
H
TRUTH TABLE FOR LOGIC
INPUTS
SHDN
H
H
H
H
H
Ø
X
X
L
¦
Communication is initiated with
device. Device comes out of
standby mode.
No action. Device is waiting for
data to be clocked into shift
register or CS to go high to
execute command.
Shift one bit into shift register.
The shift register can be loaded
while the SHDN pin is low.
Shift one bit out of shift register
on the SO pin. The SO pin is
active while the SHDN pin is
low.
Based on command bits, either
load data from shift register into
data latches or execute shut-
down command. Neither com-
mand executed unless
multiples of 16 clocks have
been entered while CS is low.
SO pin goes to a logic low.
Static Operation.
All data registers set and
latched to code 80h.
All data registers set and
latched to code 80h. Device is
in hardware shutdown mode
and will remain in this mode.
All potentiometers put into
hardware shutdown mode;
terminal A is open and W is
shorted to B.
All potentiometers exit hard-
ware shutdown mode. Potenti-
ometers will also exit software
shutdown mode if this rising
edge occurs after a low pulse
on CS. Contents of data
latches are restored.
DS11195C-page 21
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