AD5160BRJZ100-R2 Analog Devices Inc, AD5160BRJZ100-R2 Datasheet - Page 15

• Manufacturer Part Number: AD5160BRJZ100-R2
• Description: IC DGTL POT 100K I2C SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5160BRJZ100-R2

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• Track Taper: Linear
• No. Of Steps: 256
• Resistance Tolerance: ± 15%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5160EVAL - BOARD EVAL FOR AD5160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD5160BRJZ100R2TR

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by
the 256 positions of the potentiometer divider. The general
equation defining the output voltage at V
ground for any valid input voltage applied to Terminal A and
Terminal B is
For a more accurate calculation, which includes the effect of
wiper resistance, V
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors (R
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
SPI-COMPATIBLE 3-WIRE SERIAL BUS
The AD5160 contains a 3-wire SPI-compatible digital interface
(SDI, CS , and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Figure 37
V
V
W
W
(
(
D
D
)
)
=
=
).
256
R
D
WB
256
W
V
(
can be found as
D
A
)
+
V
256 −
A
256
+
R
D
DD
WA
256
V
to GND, which must be
WA
B
(
D
and R
)
V
W
Table 6
B
with respect to
WB
) and not the
.
Rev. B | Page 15 of 16
(3)
(4)
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures are shown in Figure 40 and
Figure 41. This applies to SDI, CLK, and CS , which are the
digital input pins.
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals, it is important to power V
before applying any voltage to the A, B, and W terminals;
otherwise, the diode forward biases such that V
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, V
digital inputs, and then V
V
they are powered after V
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. Keep the leads to the inputs as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Bypass supply
leads to the device with disc or chip ceramic capacitors of
0.01 μF to 0.1 μF. To minimize any transient disturbance and
low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors at the supplies (see Figure 42). To
minimize the ground bounce, join the digital ground remotely
to the analog ground at a single point.
A
, V
B
, V
W
, and the digital inputs is not important as long as
Figure 41. ESD Protection of Resistor Terminals
V
DD
Figure 40. ESD Protection of Digital Pins
C3
Figure 42. Power Supply Bypassing
+
10μF
A,B,W
DD
C1
A/B/W
340Ω
/GND.
GND
0.1μF
GND
. The relative order of powering
LOGIC
V
DD
AD5160
GND
DD
is powered
AD5160
DD
/GND
DD
,