PIC10F222-E/OT Microchip Technology, PIC10F222-E/OT Datasheet - Page 40

• Manufacturer Part Number: PIC10F222-E/OT
• Description: 768B Flash, 23B RAM, 4 I/O, 8bit ADC 6 SOT-23 BAG
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F222-E/OT

• Processor Series: PIC10F
• Core: RISC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 512 B
• Data Ram Size: 23 B
• Interface Type: RS-232, USB
• Maximum Clock Frequency: 8 MHZ
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 2 Channel
• Operating Temperature Range: - 40 C to + 125 C
• Processor To Be Evaluated: PIC10F222
• Supply Current (max): 100 nA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: -
• Peripherals: POR, WDT
• Number Of I /o: 4
• Eeprom Size: -
• Ram Size: 23 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC10F220/222
8.5
On the PIC10F220/222 devices, the DRT runs any time
the device is powered up.
The DRT operates on an internal oscillator. The pro-
cessor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
The on-chip DRT keeps the devices in a Reset condi-
tion for approximately 1.125 ms after MCLR has
reached a logic high (V
GP3/MCLR/V
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/
or space restricted applications, as well as allowing the
use of the GP3/MCLR/V
input.
The Device Reset Time delays will vary from chip-to-
chip due to V
See AC parameters for details.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-3:
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
internal 4/8 MHz oscillator. This means that the WDT
will run even if the main processor clock has been
stopped, for example, by execution of a SLEEP instruc-
tion. During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 8.1
“Configuration Bits”). Refer to the PIC10F220/222
Programming Specification to determine how to access
the Configuration Word.
DS41270E-page 38
1.125 ms (typical)
POR Reset
Device Reset Timer (DRT)
Watchdog Timer (WDT)
PP
DD
, temperature and process variation.
as MCLR and using an external RC
DRT (DEVICE RESET TIMER
PERIOD)
DD
IH
PP
MCLR) level. Programming
to rise above V
Subsequent Resets
pin as a general purpose
10 μs (typical)
DD
min. and
8.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, a time-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, V
variations (see DC specs).
Under worst-case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
© 2007 Microchip Technology Inc.
DD
and part-to-part process
DD
= Min., Temperature