DS1856E-030+T&R Maxim Integrated Products, DS1856E-030+T&R Datasheet - Page 14

• Manufacturer Part Number: DS1856E-030+T&R
• Description: IC RES TEMP-CNTRL 30/10K 16TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1856E-030+T&R

• Taps: 256
• Resistance (ohms): 10K, 30K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.85 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 10K, 30K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
14
(hex)
(hex)
Row
Byte
00
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
28
30
38
40
48
50
58
____________________________________________________________________
<0>
<1>
<1>
<1>
<1>
<1>
Temp Alarm
<1>
<1>
<1>
<1>
<1>
<1>
<1>
Temp Warn
<2>
User ROM
User ROM
User ROM
User ROM
User ROM
User ROM
User ROM
Volt Alarm
<2>
<0>
Table Select
Volt Warn
Threshold
Threshold
Threshold
Threshold
Threshold
User EE
user ROM
user ROM
user ROM
user ROM
user ROM
user ROM
user ROM
Alrm Wrn
Name
Name
Values
Values
Byte
Row
0
1
0
1
2
3
4
<6>
bit
2
2
S
S
Byte 0/8
Reserved
15
15
15
Alarm
Bit7
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
Temp Alarm Hi
Mon1 Alarm Hi
Mon2 Alarm Hi
Mon3 Alarm Hi
<2>
V
Temp Value
CC
bit
Mon3 Value
1
2
2
2
2
Word 0
14
14
14
6
6
Alarm Hi
<6>
bit
2
2
2
2
Byte 1/9
Reserved
13
13
Alarm
13
5
5
Bit6
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
bit
2
2
0
2
2
12
12
12
4
4
<6>
bit
2
2
Reserved
2
2
Byte 2/A
Reserved
11
11
11
3
3
EXPANDED BYTES
LOWER MEMORY
Bit5
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
Temp Alarm Lo
Mon1 Alarm Lo
Mon2 Alarm Lo
Mon3 Alarm Lo
V
<2>
bit
CC
Vcc Value
2
2
2
2
Reserved
10
10
Word 1
10
2
2
Alarm Lo
bit
Reserved
2
2
2
2
Byte 3/B
1
1
9
9
9
Bit4
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
<6>
bit
2
2
2
2
PWE msb
0
0
8
8
8
bit
2
2
2
2
Byte 4/C
-1
-1
7
7
Warn
7
Bit3
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
Temp Warn Hi
Mon1 Warn Hi
Mon2 Warn Hi
Mon3 Warn Hi
V
<2>
Mon1 Value
bit
CC
1
2
2
2
2
Word 2
Reserved
-2
-2
6
6
6
Warn Hi
bit
2
2
2
2
Byte 5/D
-3
-3
5
5
Warn
5
Bit2
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
<6>
bit
0
2
2
2
2
-4
-4
4
4
PWE lsb
4
bit
Memory Map
Reserved
2
2
2
2
Byte 6/E
<0>
-5
-5
3
3
3
Status
Bit1
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
Temp Warn Lo
Mon1 Warn Lo
Mon2 Warn Lo
Mon3 Warn Lo
V
Mon2 Value
bit
CC
2
2
2
2
Word 3
-6
-6
2
2
2
Warn Lo
bit
<3>
Reserved
2
2
<5>
2
2
Byte 7/F
-7
-7
1
1
1
Update
Tbl Sel
Bit0
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
bit
2
2
2
2
-8
-8
0
0
0