DS1868-50+ Maxim Integrated Products, DS1868-50+ Datasheet - Page 2
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DS1868-50+
Manufacturer Part Number
DS1868-50+
Description
IC POT DIGITAL DUAL 50K 14-DIP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1868-10.pdf
(14 pages)
Specifications of DS1868-50+
Taps
256
Resistance (ohms)
50K
Number Of Circuits
2
Temperature Coefficient
750 ppm/°C Typical
Memory Type
Volatile
Interface
3-Wire Serial
Voltage - Supply
2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DS1868
wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device is accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same
resolution. For multiple-device, single-processor environments, the DS1868 can be cascaded or daisy
chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1868 is offered in three standard resistance values which include 10, 50, and 100 kohm versions.
The part is available in 16-pin SOIC (300-mil), 14-pin DIP, and 20-pin (173-mil) TSSOP packages.
OPERATION
The DS1868 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper
positions and the stack select bit when the device is powered. A block diagram of the DS1868 is
presented in Figure 1.
Communication and control of the DS1868 is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:
,
RST
CLK, and DQ.
The
control signal is used to enable the 3-wire serial port operation of the device. The
signal is
RST
RST
an active high input and is required to begin any communication to the DS1868. The CLK signal input is
used to provide timing synchronization for data input and output. The DQ signal line is used to transmit
potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the
DS1868.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the
RST
signal input is low. Communication with the DS1868 requires the transition of the
input from a low
RST
state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to
high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing
diagrams of Figure 9(b),(c).
Data written to the DS1868 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position
with the MSB for the wiper position occupying bit 9 and the LSB bit 16.
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