DS1868E-50+T&R Maxim Integrated Products, DS1868E-50+T&R Datasheet - Page 3
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DS1868E-50+T&R
Manufacturer Part Number
DS1868E-50+T&R
Description
IC POT DIGITAL DUAL 50K 20-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1868-10.pdf
(14 pages)
Specifications of DS1868E-50+T&R
Taps
256
Resistance (ohms)
50K
Number Of Circuits
2
Temperature Coefficient
750 ppm/°C Typical
Memory Type
Volatile
Interface
3-Wire Serial
Voltage - Supply
2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DS1868
DS1868 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1868, 17 bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed the
signal input should be taken to a low
RST
state to prevent any inadvertent changes to the device shift register. Once
has reached a low state,
RST
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a
transition to the inactive state. On device power-up,
RST
wiper position will be random.
STACKED CONFIGURATION
The potentiometers of the DS1868 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as R
/256 (per potentiometer); where
TOT
R
equals the total potentiometer resistance.
TOT
The wiper output for the combined stacked potentiometer will be taken at the S
pin, which is the
OUT
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
OUT
shift register. If the stack select bit has value 0, the multiplexed output, S
, will be that of the
OUT
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