CAT5411WI-25-T1 ON Semiconductor, CAT5411WI-25-T1 Datasheet - Page 10

• Manufacturer Part Number: CAT5411WI-25-T1
• Description: IC POT DPP 2.5K 64TAP SPI 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5411WI-25-T1

• Taps: 64
• Resistance (ohms): 2.5K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 2.5K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

illustrated in Figure 8. These three−byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t
A transfer from the WCR (current wiper position), to a Data
Register is a write to non−volatile memory and takes a
minimum of t
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the CAT5411;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
•
•
The basic sequence of the three byte instructions is
Four instructions require a two−byte sequence to
XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
SI
SI
ID3 ID2 ID1 ID0
ID3 ID2 ID1
WR
0
0
Device ID
Device ID
1
to complete. The transfer can occur
1
0
SI
0
1
ID0
1
A3
0
ID3
A3
0
0
Figure 9. Increment/Decrement
A2 A1 A0
Address
0
Internal
Device ID
Address
A2 A1 A0
Internal
ID2
0
1
Figure 8. Three−Byte Instruction Sequence
Figure 7. Two−Byte Instruction Sequence
ID1
0
ID0
1
I3
A3
Instruction
0
I3
Opcode
I2 I1 I0 R1 R0
Instruction
A2
Address
Internal
Opcode
http://onsemi.com
0
I2
WRL
A1
I1
.
A0
Register
Address
10
I0
Data
I3
Register
Address
•
•
Increment/Decrement Command
and 10). The Increment/Decrement command is different
from the other commands. Once the command is issued the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCK clock pulse (t
HIGH, the selected wiper will move one resistor segment
towards the R
pulse while SI is LOW, the selected wiper will move one
resistor segment towards the R
Instruction
R1
Data
Opcode
The final command is Increment/Decrement (Figures 9
See Instructions format for more detail.
Instruction
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control Registers
to the specified associated Data Registers.
I2
0 P0
R0 0
Pot/WCR
Address
I1 I0 R1 R0 0
Pot/WCR
Address
D7 D6 D5 D4 D3 D2 D1 D0
P0
Register
Address
H
Sequence
terminal. Similarly, for each SCK clock
N
C
1
I
Data Register D[7:0]
N
C
2
I
Pot/WCR
WCR[7:0]
Address
P0
or
N
C
n
I
L
terminal.
D
E
C
1
HIGH
D
E
C
n
) while SI is