CAT5419WI-50-T1 ON Semiconductor, CAT5419WI-50-T1 Datasheet - Page 10

• Manufacturer Part Number: CAT5419WI-50-T1
• Description: IC POT DPP 50K 64TAP 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5419WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Number Of Elements: 2
• # Of Taps: 64
• Resistance (max): 50KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CAT5419
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by t
wiper position), to a Data Register is a write to non-
volatile memory and takes a maximum of t
complete. The transfer can occur between one of the
potentiometers and one of its associated registers; or
the transfer can occur between all potentiometers and
one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5419; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
— XFR Wiper Control Register to Data Register
Figure 7. Two-Byte
Figure 8. Three-Byte Instruction Sequence
Figure 9. Increment/Decrement
Doc. No. MD-2115 Rev. J
SDA
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
SDA
S
T
A
R
T
S
T
A
R
T
WRL
ID3 ID2 ID1 ID0
ID3 ID2 ID1 ID0
0
0
Device ID
. A transfer from the WCR (current
Device ID
1
1
SD
Instruction
0
0
A
1
1
A3
S
T
A
R
T
A3
ID3 ID2 ID1 ID0
0
A2
Internal
Address
A2 A1 A0
Device ID
Internal
Address
1
Sequence
Instruction
A1
0
A0 A
1
C
K
A3
A
C
K
I3
A2
Sequence
I3
Internal
Address
Instruction
Opcode
WR
I2
A1
Instruction
Opcode
I2
I1 I0
to
A0
I1
10
A
C
K
I0
R1 R0
— Global XFR Data Register to Wiper Control
— Global XFR Wiper Counter Register to Data
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the CAT5419 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby providing a fine tuning capability to the host.
For each SCL clock pulse (t
the selected wiper will move one resistor segment
towards the R
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R
See Instructions format for more detail.
Data
Register
Address
I3
Data
Register
Address
R1
Instruction
Opcode
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
I2
R0
Address
Pot/WCR
I1
0 P0 A
Pot/WCR
Address
0
I0
P0
C
K
H
Register
Address
R1 R0
terminal. Similarly, for each SCL clock
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
N
C
1
I
0
Data Register D[7:0]
Pot/WCR
Address
N
C
2
P0
I
Characteristics subject to change without notice
WCR[7:0]
HIGH
A
C
K
or
N
C
n
) while SDA is HIGH,
I
S
T
O
P
2009 SCILLC. All rights reserved.
L
D
E
C
1
terminal.
D
E
C
n
A
C
K
O
S
T
P
S
T
O
P