CAT5401WI-25-T1 ON Semiconductor, CAT5401WI-25-T1 Datasheet - Page 8

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CAT5401WI-25-T1

Manufacturer Part Number
CAT5401WI-25-T1
Description
IC POT DPP QUAD 64TAP SPI 24SOIC
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT5401WI-25-T1

Taps
64
Resistance (ohms)
2.5K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI Serial
Voltage - Supply
2.5 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resistance In Ohms
2.5K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Instruction and Register Description
Device Type / Address Byte
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5401 are fixed at
0101[B] (refer to Figure 4).
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the
A1 − A0 input pins for the CAT5401 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent by the
master executes the instruction. The A1 − A0 inputs can be
actively driven by CMOS input signals or tied to V
V
be set to 0.
SS
The first byte sent to the CAT5401 from the master/
The two least significant bits in the slave address byte, A1
. The remaining two bits in the device address byte must
(MSB)
(MSB)
ID3
I3
0
ID2
I2
1
DeviceType
Instruction
Identifier
Opcode
ID1
Figure 4. Identification Byte Format
I1
Figure 5. Instruction Byte Format
0
http://onsemi.com
CC
ID0
I0
or
1
8
Instruction Byte
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format is
shown in Figure 5.
Table 11. DATA REGISTER SELECTION
R1
The next byte sent to the CAT5401 contains the
0
Data Register
Selection
Data Register Selected
R0
SlaveAddress
0
DR0
DR1
DR2
DR3
WCR/Pot Selection
P1
A1
(LSB)
(LSB)
A0
P0
R1
0
0
1
1
R0
0
1
0
1

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