AD5204BRU100-REEL7 Analog Devices Inc, AD5204BRU100-REEL7 Datasheet - Page 16
![IC DGTL POT QUAD 256POS 24-TSSOP](/photos/6/60/66036/ru-24_sml.jpg)
AD5204BRU100-REEL7
Manufacturer Part Number
AD5204BRU100-REEL7
Description
IC DGTL POT QUAD 256POS 24-TSSOP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5204BRUZ50.pdf
(20 pages)
Specifications of AD5204BRU100-REEL7
Rohs Status
RoHS non-compliant
Taps
256
Resistance (ohms)
100K
Number Of Circuits
4
Temperature Coefficient
700 ppm/°C Typical
Memory Type
Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
100K
Number Of Elements
4
# Of Taps
256
Resistance (max)
100KOhm
Power Supply Requirement
Single/Dual
Interface Type
Serial (3-Wire/SPI)
Single Supply Voltage (typ)
3/5V
Dual Supply Voltage (typ)
±2.5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
±2.3V
Dual Supply Voltage (max)
±2.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Not Compliant
Other names
AD5204BRU100REEL7
AD5204/AD5206
TEST CIRCUITS
Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
V+
I
MS
DUT
B
A
Figure 26. ESD Protection of Resistor Terminals
W
Figure 28. Resistor Position Nonlinearity Error
I
Figure 25. ESD Protection of Digital Pins
V+
W
Figure 29. Wiper Resistance Test Circuit
=
(Rheostat Operation; R-INL, R-DNL)
NO CONNECT
V
W
A, B, W
1V/R
V
MS
NOMINAL
340kΩ
DUT
DUT
A
B
A
B
W
W
V
SS
V
V+
R
WHERE V
AND V
SS
W
V
MS
=
V
LOGIC
V+ = V
1LSB = V+/256
W2
V
DD
W2
I
V
W
MS
W1
= V
– [V
DD
= V
MS
W1
MS
WHEN I
+ I
WHEN I
I
W
W
(R
W
AW
= 1/R
W
II R
= 0
BW
)]
Rev. C | Page 16 of 20
V+
Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)
Figure 32. Noninverting Programmable Gain Test Circuit
OFFSET
Figure 31. Inverting Programmable Gain Test Circuit
~
OFFSET
Figure 34. Incremental On-Resistance Test Circuit
OFFSET
GND
V
GND
GND
DD
Figure 33. Gain vs. Frequency Test Circuit
V
IN
A
B
V
DUT
A
W
B
DUT
W
A
V
IN
V
OFFSET BIAS
V
2.5V
OFFSET BIAS
MS
IN
V
DUT
SS
B
I
A
A
SW
W
TO V
CODE = 0x00
DUT
R
W
W
B
SW
DD
OP279
=
V+ = V
PSRR (dB) = 20 log
PSS (%/%) =
OP42
OP279
B
0.1V
I
+15V
–15V
SW
+
–
5V
DD
5V
0.1V
± 10%
∆V
∆V
V
V
MS
DD
OUT
OUT
V
%
%
OUT
(
∆V
∆V
MS
DD
)