LTC1329CS8-50#PBF Linear Technology, LTC1329CS8-50#PBF Datasheet - Page 7

• Manufacturer Part Number: LTC1329CS8-50#PBF
• Description: IC D/A CONV 8BIT MICROPWR 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1329CS8-50#PBF

• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 840µW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

APPLICATIONS
Standard 3-Wire Mode (Figure 3)
Refer to the Serial Interface Operating Sequence in Figure
1. When operating in 3-wire mode, the LTC1329-10/
LTC1329-50/LTC1329A-50 will interface directly with most
standard 3- or 4-wire serial interface systems. The clock
(CLK) input synchronizes the data transfer with each input
bit captured at the rising edge of CLK and each output data
bit shifted out through D
edge at CS initiates the data transfer and brings the D
pin out of three-state. The serial 8-bit data representing the
new DAC setting is shifted into the D
neously, the previous DAC setting is shifted out of the
D
CS transfers the data from the input shift register into the
DAC register. The DAC output assumes the new value and
the D
1-Wire Interface (Pulse Mode, Figure 4)
In 1-wire pulse mode, each rising edge at CLK increments
the upper six bits of the DAC register by one count. When
incramented beyond 11111100B, the counter rolls over
and sets the DAC to the minimum value (00000000B). In
this way, a single pulse applied to CLK increases the DAC
output by a single 4-LSB step and 63 pulses decrease the
DAC output by one step. The last two LSBs are always zero
in pulse mode.
To configure the LTC1329-10/LTC1329-50/LTC1329A-50
in 1-wire pulse mode, tie both the CS and D
OUT
I
I
OUT
OUT
OUT
pin. After the new data is shifted in, a rising edge at
0.1 F
V
D
FOR HALF DUPLEX DATA TRANSFER
CC
IN
= (B7 B6 B5 B4 B3 B2 B1 B0)I
= (B7 B6 B5 B4 B3 B2 0 0)I
AND D
pin returns to a high-impedance state.
Figure 3. 3-Wire Mode; Serial Interface
(3-Wire Control by CS, CLK and D
OUT
SHDN
CAN BE TIED TOGETHER
I
D
OUT
CLK
OUT
D
CS
IN
U
1
2
3
4
I
V
SHDN
CLK
OUT
CC
INFORMATION
OUT
U
LTC1329
at the falling edge. A falling
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
D
GND
OUT
D
CS
IN
FULLSCALE
W
6
5
8
7
FULLSCALE
IN
1329 F03
IN
IN
)
pin. Simulta-
/255
pins to V
U
/255
OUT
CC
.
2-Wire Interface (Pulse Mode, Figure 5)
In 2-wire pulse mode, a logic HIGH at UP/DN programs the
DAC register to increment and each rising edge at CLK
increments the upper six bits of the register by one count.
Similarly, a logic LOW at UP/DN set the DAC register to
decrement and a rising edge at CLK decrements the upper
six bits of the register by one count. Each count in 2-wire
mode changes the DAC output by a single four LSB step.
The DAC register stops incramenting at 11111100B and
stops decrementing at 00000000B and will not roll over in
2-wire pulse mode. The last two LSBs are always zero in
pulse mode.
To configure the LTC1329-10/LTC1329-50/LTC1329A-50
in 2-wire pulse mode, tie CS to V
pin low at least once during power-up.
I
OUT
V
0.1 F
V
0.1 F
= (B7 B6 B5 B4 B3 B2 0 0)I
CC
CC
Figure 5. Pulse Mode; Increment/Decrement
(2-Wire Control by CLK and UP/DN)
LTC1329-50/LTC1329A-50
Figure 4. Pulse Mode: Increment Only
(1-Wire Control by CLK)
UP/DN
SHDN
SHDN
I
I
CLK
CLK
OUT
OUT
1
2
3
4
1
2
3
4
I
V
SHDN
CLK
I
V
SHDN
CLK
OUT
OUT
CC
CC
LTC1329
LTC1329
D
D
GND
GND
OUT
OUT
D
D
CC
CS
CS
IN
IN
FULLSCALE
LTC1329-10/
and bring the UP/DN
6
5
6
5
8
7
8
7
1329 TA04
1329 F04
/255
7