AD9762ARUZ Analog Devices Inc, AD9762ARUZ Datasheet
AD9762ARUZ
Specifications of AD9762ARUZ
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AD9762ARUZ Summary of contents
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FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 70 dBc Differential Current Outputs Power Dissipation: 175 ...
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AD9762–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL +25° MIN MAX Differential Nonlinearity (DNL +25° MIN MAX ANALOG OUTPUT Offset ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to ...
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AD9762 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V Logic “1” Voltage @ DVDD = +3 V Logic “0” Voltage @ DVDD = +5 V Logic “0” Voltage @ DVDD = +3 V Logic “1” ...
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Pin No. Name Description 1 DB11 Most Significant Data Bit (MSB). 2–11 DB10–DB1 Data Bits 1–10. 12 DB0 Least Significant Data Bit (LSB). 13, 14 Internal Connection. 15 SLEEP Power-down Control Input. Active High. Contains active pull-down ...
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AD9762 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. ...
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Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = + mA, 50 OUTFS 90 25MSPS 80 5MSPS 50MSPS 70 100MSPS 60 125MSPS 50 0 100 FREQUENCY – MHz Figure ...
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AD9762 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 –90 4TH HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 12. THD vs CLOCK MHz OUT 1.25 1.00 0.75 0.50 ...
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Typical AC Characterization Curves @ +3 V Supplies = 20 mA, 50 Ω Doubly Terminated Load, Differential Output, T (AVDD = +3 V, DVDD = + OUTFS 90 80 5MSPS 25MSPS 70 50MSPS 100MSPS 60 125MSPS 50 0.1 ...
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AD9762 –70 –75 2ND HARMONIC 3RD –80 HARMONIC –85 4TH –90 HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 30. THD vs CLOCK OUT 2 MHz 1.25 1.00 0.75 0.50 ...
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FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9762. The AD9762 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 ...
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AD9762 REFERENCE OPERATION The AD9762 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external refer- ence. REFIO serves as either an input or output depending on whether the internal or an external ...
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AVDD 1.2V AD1580 The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and I varied by an external voltage applied fier. An example of this ...
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AD9762 I and I also have a negative and positive voltage OUTA OUTB compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of –1 set by the breakdown limits ...
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I – mA OUTFS Figure 47. I vs. I AVDD Conversely dependent on both the digital input wave- DVDD form and digital supply ...
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AD9762 DIFFERENTIAL USING AN OP AMP An op amp can also be used to perform a differential to single- ended conversion as shown in Figure 51. The AD9762 is configured with two equal load resistors, R The differential voltage developed ...
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For those applications that require a single + supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 55. The circuit consists of a differential ...
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AD9762 REFLO REFIO IOUTA U1 I-CHANNEL FS ADJ IOUTB R SET CLOCK 2k * CLOCK R CAL1 AVDD 50 REFLO CLOCK IOUTA REFIO U2 0.1 F Q-CHANNEL FS ADJ IOUTB R SET CAL2 * OHMTEK ORNA1001F 100 ...
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REV. B Figure 59. AD9762 Evaluation Board Schematic –19– AD9762 ...
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AD9762 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) –20– REV. B ...
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REV. B Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) –21– AD9762 ...
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AD9762 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom –22– REV. B ...
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PIN 1 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 ...